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high performance narrow-band transceiver ic adf7021 rev. a informat responsi rights of license is trademar u.s.a. .com served. ion furnished by analog devices is believed to be accurate and reliable. however, no bility is assumed by analog devices for its use, nor for any infringements of patents or other third parties that may result from its use. specifications subject to change without notice. no granted by implication or otherwise under any patent or patent rights of analog devices. ks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, tel: 781.329.4700 www.analog fax: 781.461.3113 ?2007 analog devices, inc. all rights re 05876-001 features low power, narrow-band transceiver frequency bands using dual vco 80 mhz to 650 mhz 862 mhz to 950 mhz modulation schemes 2fsk, 3fsk, 4fsk, msk spectral shaping gaussian and raised cosine filtering data rates supported 0.05 kbps to 32.8 kbps 2.3 v to 3.6 v power supply programmable output power ?16 dbm to +13 dbm in 63 steps automatic pa ramp control receiver sensitivity ?130 dbm at 100 bps, 2fsk ?122 dbm at 1 kbps, 2fsk ?113 dbm at 25 kbps, raised cosine 2fsk patent pending, on-chip image rejection calibration on-chip vco and fractional-n pll on-chip, 7-bit adc and temperature sensor fully automatic frequency control loop (afc) digital received signal strength indication (rssi) integrated tx/rx switch 0.1 a leakage current in power-down mode applications narrow-band standards etsi en 300 220, fcc part 15, fcc part 90, fcc part 95, arib std-t67 low cost, wireless data transfer remote control/security systems wireless metering private mobile radio wireless medical telemetry service (wmts) keyless entry home automation process and building control pagers functional block diagram tx/rx control afc 2fsk 3fsk 4fsk demodulator clock and data recovery control rssi/ 7-bit adc gain div r rfout lna pfd cp osc1 osc2 n/n + 1 div p temp sensor osc clk div clkout test mux vcoin cpout ldo(1:4) muxout rset creg(1:4) r lna r fin r finb ce txrxclk swd txrxdata serial port sle sdata sread sclk if filter - modulator pa ramp l1 l2 log amp mux agc control 2fsk 3fsk 4fsk mod control gaussian/ raised cosine filter 3fsk encoding mux 1/2 vco1 vco2 2 figure 1.
adf7021 rev. a | page 2 of 64 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 3 ? general description ......................................................................... 4 ? specifications ..................................................................................... 5 ? rf and pll specifications ........................................................... 5 ? transmission specifications ........................................................ 6 ? receiver specifications ................................................................ 8 ? digital specifications ................................................................. 10 ? general specifications ............................................................... 11 ? timing characteristics .............................................................. 11 ? absolute maximum ratings .......................................................... 15 ? esd caution ................................................................................ 15 ? pin configuration and function descriptions ........................... 16 ? typical performance characteristics ........................................... 18 ? frequency synthesizer ................................................................... 22 ? reference input ........................................................................... 22 ? muxout .................................................................................... 23 ? voltage controlled oscillator (vco) ...................................... 24 ? choosing channels for best system performance ................. 25 ? transmitter ...................................................................................... 26 ? rf output stage .......................................................................... 26 ? modulation schemes .................................................................. 26 ? spectral shaping ......................................................................... 28 ? modulation and filtering options ........................................... 29 ? transmit latency ........................................................................ 29 ? test pattern generator ............................................................... 29 ? receiver section .............................................................................. 30 ? rf front end ............................................................................... 30 ? if filter ......................................................................................... 30 ? rssi/agc .................................................................................... 31 ? demodulation, detection, and cdr ....................................... 32 ? receiver setup ............................................................................. 34 ? demodulator considerations ................................................... 36 ? afc operation ........................................................................... 36 ? automatic sync word detection (swd) ................................ 37 ? applications information .............................................................. 38 ? if filter bandwidth calibration ............................................... 38 ? lna/pa matching ...................................................................... 38 ? image rejection calibration ..................................................... 39 ? packet structure and coding .................................................... 41 ? programming after initial power-up ..................................... 41 ? applicatons circuit .................................................................... 44 ? serial interface ................................................................................ 45 ? readback format ........................................................................ 45 ? interfacing to microcontroller/dsp ........................................ 46 ? register 0n register ............................................................... 47 ? register 1vco/oscillator register ...................................... 48 ? register 2transmit modulation register ............................ 49 ? register 3transmit/receive clock register ........................ 50 ? register 4demodulator setup register ............................... 51 ? register 5if filter setup register ......................................... 52 ? register 6if fine cal setup register ................................... 53 ? register 7readback setup register ...................................... 54 ? register 8power-down test register .................................. 55 ? register 9agc register ......................................................... 56 ? register 10afc register ....................................................... 57 ? register 11sync word detect register ................................ 58 ? register 12swd/threshold setup register ........................ 58 ? register 133fsk/4fsk demod register ............................. 59 ? register 14test dac register ............................................... 60 ? register 15test mode register ............................................. 61 ? outline dimensions ....................................................................... 62 ? ordering guide .......................................................................... 62 ?
adf7021 rev. a | page 3 of 64 revision history 9/07rev. 0 to rev. a change to uart/spi mode section............................................. 14 changes to figure 10 ...................................................................... 16 change to table 8 ............................................................................ 16 changes to figure 12 ...................................................................... 18 change to internal inductor vco section .................................. 24 changes to figure 40 ...................................................................... 26 changes to figure 47 ...................................................................... 32 change to table 19 .......................................................................... 34 changes to figure 56 ...................................................................... 44 change to spi mode section ......................................................... 46 changes to figure 59 ...................................................................... 46 changes to figure 60 ...................................................................... 46 change to register 3transmit/receive clock register section ............................................................................... 50 change to register 4demodulator setup register section ............................................................................... 51 change to register 7readback setup register ........................ 54 change to register 133fsk/4fsk demod register heading ............................................................................. 59 3/07revision 0: initial version
adf7021 rev. a | page 4 of 64 general description the adf7021 is a high performance, low power, highly integrated 2fsk/3fsk/4fsk transceiver. it is designed to operate in the narrow-band, license-free ism bands, and in the licensed bands with frequency ranges of 80 mhz to 650 mhz and 862 mhz to 950 mhz. the part has both gaussian and raised cosine transmit data filtering options to improve spectral efficiency for narrow- band applications. it is suitable for circuit applications targeted at european etsi en 300 220, the japanese arib std-t67, the chinese short range device regulations, and the north american fcc part 15, part 90, and part 95 regulatory standards. a complete transceiver can be built using a small number of external discrete components, making the adf7021 very suitable for price sensitive and area sensitive applications. the range of on-chip fsk modulation and data filtering options allows users greater flexibility in their choice of modulation schemes while meeting tight spectral efficiency requirements. the adf7021 also supports protocols that dynamically switch between 2fsk/3fsk/4fsk to maximize communication range and data throughput. the transmit section contains dual voltage controlled oscillators (vcos) and a low noise fractional-n pll with an output resolution of <1 ppm. the adf7021 has a vco using an internal lc tank (431 mhz to 475 mhz, 862 mhz to 950 mhz) and a vco using an external inductor as part of its tank circuit (80 mhz to 650 mhz). the dual vco design allows dual-band operation where the user can transmit and/or receive at any frequency supported by the internal inductor vco and can also transmit and/or receive at a particular frequency band supported by the external inductor vco. the frequency agile pll allows the adf7021 to be used in frequency hopping spread spectrum (fhss) systems. both vcos operate at twice the fundamental frequency to reduce spurious emissions and frequency pulling problems. the transmitter output power is programmable in 63 steps from ?16 dbm to +13 dbm, and has an automatic power ramp control to prevent spectral splatter and help meet regulatory standards. the transceiver rf frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. the device operates with a power supply range of 2.3 v to 3.6 v and can be powered down when not in use. a low if architecture is used in the receiver (100 khz), which minimizes power consumption and the external component count, yet avoids dc offset and flicker noise at low frequencies. the if filter has programmable bandwidths of 12.5 khz, 18.75 khz, and 25 khz. the adf7021 supports a wide variety of program- mable features including rx linearity, sensitivity, and if bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. the receiver also features a patent-pending automatic frequency control (afc) loop with programmable pull-in range that allows the pll to track out the frequency error in the incoming signal. the receiver achieves an image rejection performance of 56 db using a patent-pending ir calibration scheme that does not require the use of an external rf source. an on-chip adc provides readback of the integrated tempera- ture sensor, external analog input, battery voltage, and rssi signal, which provides savings on an adc in some applications. the temperature sensor is accurate to 10c over the full operating temperature range of ?40c to +85c. this accuracy can be improved by performing a 1-point calibration at room temperature and storing the result in memory.
adf7021 rev. a | page 5 of 64 specifications v dd = 2.3 v to 3.6 v, gnd = 0 v, t a = t min to t max , unless otherwise noted. typical specifications are at v dd = 3 v, t a = 25c. all measurements are performed with the eval-adf7021dbx using the pn9 data sequence, unless otherwise noted. rf and pll specifications table 1. parameter min typ max unit test conditions/comments rf characteristics see table 9 for required vco_bias and vco_adjust settings frequency ranges (direct output) 160 650 mhz external inductor vco 862 950 mhz internal inductor vco frequency ranges (rf divide-by-2 mode) 80 325 mhz external inductor vco, rf divide-by-2 enabled 431 475 mhz internal inductor vco, rf divide-by-2 enabled phase frequency detector (pfd) frequency 1 rf/256 26/30 mhz crystal reference/external reference phase-locked loop (pll) vco gain 2 868 mhz, internal inductor vco 58 mhz/v vco_adjust = 0, vco_bias = 8 434 mhz, internal inductor vco 29 mhz/v vco_adjust = 0, vco_bias = 8 426 mhz, external inductor vco 27 mhz/v vco_adjust = 0, vco_bias = 3 160 mhz, external inductor vco 6 mhz/v vco_adjust = 0, vco_bias = 2 phase noise (in-band) 868 mhz, internal inductor vco ?97 dbc/hz 10 khz offset, pa = 10 dbm, v dd = 3.0 v, pfd = 19.68 mhz, vco_bias = 8 433 mhz, internal inductor vco ?103 dbc/hz 10 khz offset, pa = 10 dbm, v dd = 3.0 v, pfd = 19.68 mhz, vco_bias = 8 426 mhz, external inductor vco ?95 dbc/hz 10 khz offset, pa = 10 dbm, v dd = 3.0 v, pfd = 9.84 mhz, vco_bias = 3 phase noise (out-of-band) ?124 dbc/hz 1 mhz offset, f rf = 433 mhz, pa = 10 dbm, v dd = 3.0 v, pfd = 19.68 mhz, vco_bias = 8 normalized in-band phase noise floor 3 ?203 dbc/hz pll settling 40 s measured for a 10 mhz frequency step to within 5 ppm accuracy, pfd = 19.68 mhz, loop bandwidth (lbw) = 100 khz reference input crystal reference 4 3.625 26 mhz external oscillator 4 , 5 3.625 30 mhz crystal start-up time 6 xtal bias = 20 a 0.930 ms 10 mhz xtal, 33 pf load capacitors, v dd = 3.0 v xtal bias = 35 a 0.438 ms 10 mhz xtal, 33 pf load capacitors, v dd = 3.0 v input level for external oscillator 7 osc1 0.8 v p-p clipped sine wave osc2 cmos levels v adc parameters inl 0.4 lsb v dd = 2.3 v to 3.6 v, t a = 25c dnl 0.4 lsb v dd = 2.3 v to 3.6 v, t a = 25c 1 the maximum usable pfd at a particular rf freq uency is limited by the minimum n divide value. 2 vco gain measured at a vco tuning voltage of 1 v. the vco gain varies across the tuning range of the vco. the software package adisimpll ? can be used to model this variation. 3 this value can be used to calculate the in-band phase noise for any operating frequency. use the following equation to calculate the in-band phase noise performance as seen at the pa output: ?203 + 10 log(f pfd ) + 20 logn. 4 guaranteed by design. sample tested to ensure compliance. 5 a tcxo, vcxo, or ocxo can be used as an external oscillator. 6 crystal start-up time is the time from chip enable (ce) being asserted to correct clock frequency on the clkout pin. 7 refer to the reference input section for details on using an external oscillator.
adf7021 rev. a | page 6 of 64 transmission specifications table 2. parameter min typ max unit test conditions/comments data rate 2fsk, 3fsk 0.05 25 1 kbps if_bw = 25 khz 4fsk 0.05 32.8 2 kbps if_bw = 25 khz modulation frequency deviation (f dev ) 3 0.056 28.26 khz pfd = 3.625 mhz 0.306 156 khz pfd = 20 mhz deviation frequency resolution 56 hz pfd = 3.625 mhz gaussian filter bt 0.5 raised cosine filter alpha 0.5/0.7 programmable transmit power maximum transmit power 4 +13 dbm v dd = 3.0 v, t a = 25c transmit power variation vs. temperature 1 db ?40c to +85c transmit power variation vs. v dd 1 db 2.3 v to 3.6 v at 915 mhz, t a = 25c transmit power flatness 1 db 902 mhz to 928 mhz, 3 v, t a = 25c programmable step size 0.3125 db ?20 dbm to +13 dbm adjacent channel power (acp) 426 mhz, external inductor vco pfd = 9.84 mhz 12.5 khz channel spacing ?50 dbc gaussian 2fsk modulation, measured in a 4.25 khz bandwidth at 12.5 khz offset, 2.4 kbps pn9 data, 1.2 khz frequency deviation, compliant with arib std-t67 25 khz channel spacing ?50 dbc gaussian 2fsk modulation, measured in a 8 khz bandwidth at 25 khz offset, 9.6 kbps pn9 data, 2.4 khz frequency deviation, compliant with arib std-t67 868 mhz, internal inductor vco pfd = 19.68 mhz 12.5 khz channel spacing ?46 dbm gaussian 2fsk modulation, 10 db m output power, measured in a 6.25 khz bandwidth at 12.5 khz offset, 2.4 kbps pn9 data, 1.2 khz frequency deviation, compliant with etsi en 300-220 25 khz channel spacing ?43 dbm gaussian 2fsk modulation, 10 db m output power, measured in a 12.5 khz bandwidth at 25 khz offset, 9.6 kbps pn9 data, 2.4 khz frequency deviation, compliant with etsi en 300-220 433 mhz, internal inductor vco pfd = 19.68 mhz 12.5 khz channel spacing ?50 dbm gaussian 2fsk modulation, 10 db m output power, measured in a 6.25 khz bandwidth at 12.5 khz offset, 2.4 kbps pn9 data, 1.2 khz frequency deviation, compliant with etsi en 300-220 25 khz channel spacing ?47 dbm gaussian 2fsk modulation, 10 db m output power, measured in a 12.5 khz bandwidth at 25 khz offset, 9.6 kbps pn9 data, 2.4 khz frequency deviation, compliant with etsi en 300-220 occupied bandwidth 99.0% of total mean power; 12.5 khz channel spacing (2.4 kbps pn9 data, 1.2 khz frequency deviation); 25 khz channel spacing (9.6 kbps pn9 data, 2.4 khz frequency deviation) 2fsk gaussian data filtering 12.5 khz channel spacing 3.9 khz 25 khz channel spacing 9.9 khz 2fsk raised cosine data filtering 12.5 khz channel spacing 4.4 khz 25 khz channel spacing 10.2 khz 3fsk raised cosine filtering 12.5 khz channel spacing 3.9 khz 25 khz channel spacing 9.5 khz 4fsk raised cosine filtering 19.2 kbps pn9 data, 1.2 khz frequency deviation 25 khz channel spacing 13.2 khz
adf7021 rev. a | page 7 of 64 parameter min typ max unit test conditions/comments spurious emissions reference spurs ?65 dbc 100 khz loop bandwidth harmonics 5 13 dbm output power, unfiltered conductive/filtered conductive second harmonic ?35/?52 dbc third harmonic ?43/?60 dbc all other harmonics ?36/?65 dbc optimum pa load impedance 6 f rf = 915 mhz 39 + j61 f rf = 868 mhz 48 + j54 f rf = 450 mhz 98 + j65 f rf = 426 mhz 100 + j65 f rf = 315 mhz 129 + j63 f rf = 175 mhz 173 + j49 1 using gaussian or raised cosine filtering. the frequency deviation should be chosen to ensure that the transmit occupied signa l bandwidth is within the receiver if filter bandwidth. 2 using raised cosine filtering with an alpha = 0.7. the inner frequency deviation = 1.78 khz, and the post_demod_bw = 24.6 khz. 3 for the definition of frequency deviation, refer to the register 2transmit modulation register section. 4 measured as maximum unmodulated power. 5 conductive filtered harmonic emissions measured on the eval-adf 7021dbx, which includes a t-stage harmonic filter (two inductor s and one capacitor). 6 for matching details, refer to the lna/pa matching section.
adf7021 rev. a | page 8 of 64 receiver specifications table 3. parameter min typ max unit test conditions/comments sensitivity bit error rate (ber) = 10 ?3 , low noise amplifier (lna) and power amplifier (pa) matched separately 2fsk sensitivity at 0.1 kbps ?130 dbm f dev = 1 khz, high sensitivity mode, if_bw = 12.5 khz sensitivity at 0.25 kbps ?127 dbm f dev = 1 khz, high sensitivity mode, if_bw = 12.5 khz sensitivity at 1 kbps ?122 dbm f dev = 1 khz, high sensitivity mode, if_bw = 12.5 khz sensitivity at 9.6 kbps ?115 dbm f dev = 4 khz, high sensitivity mode, if_bw = 18.75 khz sensitivity at 25 kbps ?110 dbm f dev = 10 khz, high sensitivity mode, if_bw = 25 khz gaussian 2fsk sensitivity at 0.1 kbps ?129 dbm f dev = 1 khz, high sensitivity mode, if_bw = 12.5 khz sensitivity at 0.25 kbps ?127 dbm f dev = 1 khz, high sensitivity mode, if_bw = 12.5 khz sensitivity at 1 kbps ?121 dbm f dev = 1 khz, high sensitivity mode, if_bw = 12.5 khz sensitivity at 9.6 kbps ?114 dbm f dev = 4 khz, high sensitivity mode, if_bw = 18.75 khz sensitivity at 25 kbps ?111 dbm f dev = 10 khz, high sensitivity mode, if_bw = 25 khz gmsk sensitivity at 9.6 kbps ?113 dbm f dev = 2.4 khz, high sensitivity mode, if_bw = 18.75 khz raised cosine 2fsk sensitivity at 0.25 kbps ?127 dbm f dev = 1 khz, high sensitivity mode, if_bw = 12.5 khz sensitivity at 1 kbps ?121 dbm f dev = 1 khz, high sensitivity mode, if_bw = 12.5 khz sensitivity at 9.6 kbps ?114 dbm f dev = 4 khz, high sensitivity mode, if_bw = 18.75 khz sensitivity at 25 kbps ?113 dbm f dev = 10 khz, high sensitivity mode, if_bw = 25 khz 3fsk sensitivity at 9.6 kbps ?110 dbm f dev = 2.4 khz, high sensitivity mode, if_bw = 18.75 khz, viterbi detection on raised cosine 3fsk sensitivity at 9.6 kbps ?110 dbm f dev = 2.4 khz, high sensitivity mode, if_bw = 12.5 khz, alpha = 0.5, viterbi detection on sensitivity at 19.6 kbps ?106 dbm f dev = 4.8 khz, high sensitivity mode, if_bw = 18.75 khz, alpha = 0.5, viterbi detection on 4fsk sensitivity at 9.6 kbps ?112 dbm f dev (inner) = 1.2 khz, high sensitivity mode, if_bw = 12.5 khz sensitivity at 19.6 kbps ?107 dbm f dev (inner) = 2.4 khz, high sensitivity mode, if_bw = 25 khz raised cosine 4fsk sensitivity at 9.6 kbps ?109 dbm f dev (inner) = 1.2 khz, high sensitivity mode, if_bw = 12.5 khz, alpha = 0.5 sensitivity at 19.2 kbps ?103 dbm f dev (inner) = 1.2 khz, high sensitivity mode, if_bw = 18.75 khz, alpha = 0.5 sensitivity at 32.8 kbps ?100 dbm f dev (inner) = 1.8 khz, high sensitivity mode, if_bw = 25 khz, alpha = 0.7 input ip3 two-tone test, f lo = 860 mhz, f1 = f lo + 100 khz, f2 = f lo ? 800 khz low gain enhanced linearity mode ?3 dbm lna_gain = 3, mixer_linearity = 1 medium gain mode ?13.5 dbm lna_gain = 10, mixer_linearity = 0 high sensitivity mode ?24 dbm lna_gain = 30, mixer_linearity = 0
adf7021 rev. a | page 9 of 64 parameter min typ max unit test conditions/comments adjacent channel rejection 868 mhz wanted signal is 3 db above the sensitivity point (ber = 10 ?3 ); unmodulated interferer is at the center of the adjacent channel; rejection measured as the difference between interferer level and wanted signal level in db 12.5 khz channel spacing 25 db 12.5 khz if_bw 25 khz channel spacing 27 db 25 khz if_bw 25 khz channel spacing 39 db 18 khz if_bw 426 mhz, external inductor vco wanted signal 3 db above reference sensitivity point (ber = 10 ?2 ); modulated interferer (1 khz sine, 2 khz deviation) at the center of the adjacent channel; rejection measured as the difference between interferer level and reference sensitivity level in db 12.5 khz channel spacing 25 db 12.5 khz if_bw 25 khz channel spacing 30 db 25 khz if_bw 25 khz channel spacing 41 db 18 khz if_bw, compliant with arib std-t67 co-channel rejection wanted signal (2fsk, 9.6 kbps, 4 khz deviation) is 10 db above the sensitivity point (ber = 10 ?3 ), modulated interferer 868 mhz ?3 db image channel rejection wanted signal (2fsk, 9.6 kbps, 4 khz deviation) is 10 db above the sensitivity point (ber = 10 ?3 ); modulated interferer (2fsk, 9.6 kbps, 4 khz deviation) is placed at the image frequency of f rf ? 200 khz; interferer level is increased until ber = 10 ?3 900 mhz 23/39 db uncalibrated/calibrated 1 , v dd = 3.0 v, t a = 25c 450 mhz 29/50 db uncalibrated/calibrated 1 ,v dd = 3.0 v, t a = 25c 450 mhz, external inductor vco 38/53 db uncalibrated/calibrated 1 , v dd = 3.0 v, t a = 25c blocking wanted signal is 10 db above the input sensitivity level; cw interferer level is increased until ber = 10 ?3 1 mhz 69 db 2 mhz 75 db 5 mhz 78 db 10 mhz 78.5 db saturation (maximum input level) 12 dbm 2fsk mode, ber = 10 ?3 rssi range at input 2 ?120 to ?47 dbm linearity 2 db input power range = ?100 dbm to ?47 dbm absolute accuracy 3 db input power range = ?100 dbm to ?47 dbm response time 300 s see the rssi/agc section afc pull-in range 0.5 1.5 if_bw khz the range is programmable, r10_db[24:31] response time 48 bits accuracy 0.5 khz input power range = ?100 dbm to +12 dbm rx spurious emissions 3 internal inductor vco ?91/?91 dbm <1 ghz at antenna input, unfiltered conductive/filtered conductive ?52/?70 dbm >1 ghz at antenna input, unfiltered conductive/filtered conductive external inductor vco ?62/?72 dbm <1 ghz at antenna input, unfiltered conductive/filtered conductive ?64/?85 dbm >1 ghz at antenna input, unfiltered conductive/filtered conductive
adf7021 rev. a | page 10 of 64 parameter min typ max unit test conditions/comments lna input impedance rfin to rfgnd f rf = 915 mhz 24 ? j60 f rf = 868 mhz 26 ? j63 f rf = 450 mhz 63 ? j129 f rf = 426 mhz 68 ? j134 f rf = 315 mhz 96 ? j160 f rf = 175 mhz 178 ? j190 1 calibration of the image rejectio n used an external rf source. 2 for received signal levels < ?100 dbm, it is recommended to average the rssi readback value over a number of samples to improv e the rssi accuracy at low input powers. 3 filtered conductive receive spurious emi ssions measured on the eval-adf7021dbx, which includes a t-stage ha rmonic filter (two inductors and one capacitor). digital specifications table 4. parameter min typ max unit test conditions/comments timing information chip enabled to regulator ready 10 s c reg = 100 nf chip enabled to tx mode 32-bit register write time = 50 s tcxo reference 1 ms xtal 2 ms chip enabled to rx mode 32-bit register write time = 50 s, if filter coarse calibration only tcxo reference 1.2 ms xtal 2.2 ms tx to rx turnaround time 300 s + (5 t bit ) time to synchronized data out, includes agc settling and cdr synchronization; see agc information and timing section for more details; t bit = data bit period logic inputs input high voltage, v inh 0.7 v dd v input low voltage, v inl 0.2 v dd v input current, i inh /i inl 1 a input capacitance, c in 10 pf control clock input 50 mhz logic outputs output high voltage, v oh dv dd ? 0.4 v i oh = 500 a output low voltage, v ol 0.4 v i ol = 500 a clkout rise/fall 5 ns clkout load 10 pf
adf7021 rev. a | page 11 of 64 general specifications table 5. parameter min typ max unit test conditions/comments temperature range (t a ) ?40 +85 c power supplies voltage supply, v dd 2.3 3.6 v all vdd pins must be tied together transmit current consumption 1 v dd = 3.0 v, pa is matched into 50 868 mhz vco_bias = 8 0 dbm 20.2 ma 5 dbm 24.7 ma 10 dbm 32.3 ma 450 mhz, internal inductor vco vco_bias = 8 0 dbm 19.9 ma 5 dbm 23.2 ma 10 dbm 29.2 ma 426 mhz, external inductor vco vco_bias = 2 0 dbm 13.5 ma 5 dbm 17 ma 10 dbm 23.3 ma receive current consumption v dd = 3.0 v 868 mhz vco_bias = 8 low current mode 22.7 ma high sensitivity mode 24.6 ma 433mhz, internal inductor vco vco_bias = 8 low current mode 24.5 ma high sensitivity mode 26.4 ma 426 mhz, external inductor vco vco_bias = 2 low current mode 17.5 ma high sensitivity mode 19.5 ma power-down current consumption low power sleep mode 0.1 1 a ce low 1 the transmit current consumption tests used the same co mbined pa and lna match ing network as that used on the eval-adf7021dbx evaluation boards. improved pa efficiency is achieved by using a separate pa matching network. timing characteristics v dd = 3 v 10%, dgnd = agnd = 0 v, t a = 25c, unless otherwise noted. guaranteed by design but not production tested. table 6. parameter limit at t min to t max unit test conditions/comments t 1 >10 ns sdata to sclk setup time t 2 >10 ns sdata to sclk hold time t 3 >25 ns sclk high duration t 4 >25 ns sclk low duration t 5 >10 ns sclk to sle setup time t 6 >20 ns sle pulse width t 8 <25 ns sclk to sread data valid, readback t 9 <25 ns sread hold time after sclk, readback t 10 >10 ns sclk to sle disable time, readback t 11 5 < t 11 < (? t bit ) ns txrxclk negative edge to sle t 12 >5 ns txrxdata to txrxclk setup time (tx mode) t 13 >5 ns txrxclk to txrxdata hold time (tx mode) t 14 >? t bit s txrxclk negative edge to sle t 15 >? t bit s sle positive edge to positive edge of txrxclk
adf7021 rev. a | page 12 of 64 timing diagrams serial interface sclk db31 (msb) db30 db2 db1 (control bit c2) data db0 (lsb) (control bit c1) t 6 t 1 t 2 t 3 t 4 sle t 5 05876-002 s figure 2. serial interface timing diagram t 8 t 3 t 1 t 2 xr v 1 6 rv15 rv2 sclk sdata sle 05876-003 t 10 t 9 s read reg7 db0 (control bit c1) rv1 x figure 3. serial interface readback timing diagram 2fsk/3fsk timing txrxclk data t xrxdata 1 data rate/32 1/data rate 05876-004 figure 4. txrxdata/txrxclk ti ming diagram in receive mode txrxclk data txrxdata 1/data rate 05876-005 sample fetch figure 5. txrxdata/txrxclk timi ng diagram in transmit mode
adf7021 rev. a | page 13 of 64 4fsk timing in 4fsk receive mode, msb/lsb synchronization should be guaranteed by swd in the receive bit stream. rx symbol msb rx symbol lsb rx symbol msb rx symbol lsb tx symbol msb tx symbol lsb txrxdata txrxclk sle rx mode register 0 write switch from rx to tx tx/rx mode tx mode tx symbol msb t 11 t 12 t 13 t bit t symbol 05 876-074 figure 6. receive-to-transmit timing diagram in 4fsk mode tx symbol msb tx symbol lsb tx symbol msb tx symbol lsb rx symbol lsb rx symbol msb txrxdata txrxclk sle tx mode register 0 write switch from tx to rx tx/rx mode rx mode t 15 t 14 t bit t symbol 05876-075 figure 7. transmit-to-receive timing diagram in 4fsk mode
adf7021 rev. a | page 14 of 64 uart/spi mode uart mode is enabled by setting r0_db28 to 1. spi mode is enab led by setting r0_db28 to 1 and setting r15_db[17:19] to 0x7. the transmit/receive data clock is available on the clkout pin. tx bit tx bit tx bit tx bit txrxclk (transmit data input in uart/spi mode.) clkout (transmit/receive data clock in spi mode. not used in uart mode.) tx mode tx/rx mode txrxdata (receive data output in uart/spi mode.) high-z tx bit t bit fetch sample 6-082 0587 figure 8. transmit timing diagram in uart/spi mode rx bit rx bit rx bit rx bit txrxclk (transmit data input in uart/spi mode.) clkout (transmit/receive dat a clock in spi mode. not used in uart mode.) rx mode tx/rx mode txrxdata (receive data output in uart/spi mode.) high-z rx bit t bit fetch sample 05876-078 figure 9. receive timing diagram in uart/spi mode
adf7021 rev. a | page 15 of 64 absolute maximum ratings t a = 25c, unless otherwise noted. table 7. parameter rating v dd to gnd 1 ?0.3 v to +5 v analog i/o voltage to gnd ?0.3 v to av dd + 0.3 v digital i/o voltage to gnd ?0.3 v to dv dd + 0.3 v operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +125c maximum junction temperature 150c mlf ja thermal impedance 26c/w reflow soldering peak temperature 260c time at peak temperature 40 sec stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. this device is a high performance rf integrated circuit with an esd rating of <2 kv and it is esd sensitive. proper precautions should be taken for handling and assembly. esd caution 1 gnd = cpgnd = rfgnd = dgnd = agnd = 0.
adf7021 rev. a | page 16 of 64 05876-006 pin configuration and fu nction descriptions 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 adf7021 top view (not to scale) vcoin creg1 vdd1 rfout rfgnd rfin rfinb r lna vdd4 rset creg4 gnd4 mix_i mix_i mix_q mix_q filt_i filt_i gnd4 filt_q filt_q gnd4 test_a ce clkout txrxclk txrxdata swd vdd2 creg2 adcin gnd2 sclk sread sdata sle cvco gnd1 l1 gnd l2 vdd cpout creg3 vdd3 osc1 osc2 muxout 1 2 3 4 5 6 7 8 9 10 11 12 pin 1 indicator figure 10. pin configuration table 8. pin function descriptions pin no. mnemonic description 1 vcoin the tuning voltage on this pin deter mines the output frequency of the voltage controlled oscillator (vco). the higher the tuning voltage, the higher the output frequency. 2 creg1 regulator voltage for pa block. place a series 3.9 resistor and a 100 nf capacitor between this pin and ground for regulator stability and noise rejection. 3 vdd1 voltage supply for pa block. place deco upling capacitors of 0.1 f and 100 pf as close as possible to this pin. tie all vdd pins together. 4 rfout the modulated signal is available at this pin. output power levels are from ?16 dbm to +13 dbm. the output should be impedance matched to the desire d load using suitable components (see the transmitter section). 5 rfgnd ground for output stage of transmit ter. all gnd pins should be tied together. 6 rfin lna input for receiver section. input matching is re quired between the antenna and the differential lna input to ensure maximum power transfer (see the lna/pa matching section). 7 rfinb complementary lna input (see the lna/pa matching section). 8 r lna external bias resistor for lna. optimum resistor is 1.1 k with 5% tolerance. 9 vdd4 voltage supply for lna/mixer block. this pin sh ould be decoupled to ground with a 10 nf capacitor. 10 rset external resistor. sets charge pump current and some internal bias currents. use a 3.6 k resistor with 5% tolerance. 11 creg4 regulator voltage for lna/mixer block. place a 100 nf capacitor between this pin and gnd for regulator stability and noise rejection. 12, 19, 22 gnd4 ground for lna/mixer block. 13 to 18 mix_i, mix_i , mix_q, mix_q , filt_i, filt_i signal chain test pins. these pins are high impedance under normal conditions and should be left unconnected. 20, 21, 23 filt_q, filt_q , test_a signal chain test pins. these pins are high impedance under normal conditions and should be left unconnected. 24 ce chip enable. bringing ce low puts the adf7021 into complete power-down. register values are lost when ce is low, and the part must be repr ogrammed once ce is brought high. 25 sle load enable, cmos input. when sle goes high, the data st ored in the shift registers is loaded into one of the four latches. a latch is selected using the control bits. 26 sdata serial data input. the serial data is loaded msb first with the 4 lsbs as the control bits. this pin is a high impedance cmos input. 27 sread serial data output. this pin is used to feed readback data from the adf7021 to the microcontroller. the sclk input is used to clock each readback bit (for example, afc or adc) from the sread pin. 28 sclk serial clock input. this serial clock is used to clock in the serial data to the registers. the data is latched into the 32-bit shift register on the clk rising edge. this pin is a digital cmos input.
adf7021 rev. a | page 17 of 64 pin no. mnemonic description 29 gnd2 ground for digital section. 30 adcin analog-to-digital converter input. the internal 7-bit adc can be accessed through this pin. full scale is 0 v to 1.9 v. readback is made using the sread pin. 31 creg2 regulator voltage for digital block. place a 100 nf ca pacitor between this pin and ground for regulator stability and noise rejection. 32 vdd2 voltage supply for digital block. place a decoupli ng capacitor of 10 nf as close as possible to this pin. 33 swd sync word detect. the adf7021 asserts this pin when it has found a match for the sync word sequence (see the register 11sync word detect register section). this provides an interrupt for an external microcontroller indicating valid data is being received. 34 txrxdata transmit data input/received data ou tput. this is a digital pin and normal cmos levels apply. in uart/spi mode, this pin provides an output for the received data in receive mode. in transmit uart/spi mode, this pin is high impedance (see the interfacing to microcontroller/dsp section). 35 txrxclk outputs the data clock in both receive and transmit mo des. this is a digital pin and normal cmos levels apply. the positive clock edge is matched to the cent er of the received data. in transmit mode, this pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. in uart/spi mode, this pin is used to input the transmit data in transmit mode. in receive uart/spi mode, this pin is high impedance (see the interfacing to microcontroller/dsp section). 36 clkout a divided-down version of the crystal re ference with output driver. the digita l clock output can be used to drive several other cmos inputs such as a microcontroller clock. the output has a 50:50 mark-space ratio and is inverted with respect to the reference. place a series 1 k resistor as close as possible to the pin in applications where the clkout feature is being used. 37 muxout provides the digital_lock_detect signal. this signal is used to determine if the pll is locked to the correct frequency. it also provides other sign als such as regulator_ready, which is an indicator of the status of the serial interface regulator (see the muxout section for more information). 38 osc2 connect the reference crystal between this pin and osc1. a tcxo reference can be used by driving this pin with cmos levels and disabling the internal crystal oscillator. 39 osc1 connect the reference crystal between this pin and osc2. a tcxo reference can be used by driving this pin with ac-coupled 0.8 v p-p levels and by enabling the internal crystal oscillator. 40 vdd3 voltage supply for the charge pump and pll dividers . decouple this pin to ground with a 10 nf capacitor. 41 creg3 regulator voltage for charge pump and pll dividers. place a 100 nf capacitor between this pin and ground for regulator stability and noise rejection. 42 cpout charge pump output. this output generates current pu lses that are integrated in the loop filter. the integrated current changes the control voltage on the input to the vco. 43 vdd voltage supply for vco tank circuit. decoup le this pin to ground with a 10 nf capacitor. 44, 46 l2, l1 external vco inductor pins. if using an external vco inductor, connect a ch ip inductor across these pins to set the vco operating frequency. if using the internal vc o inductor, these pins can be left floating. see the voltage controlled oscillator (vco) section for more information. 45, 47 gnd, gnd1 grounds for vco block. 48 cvco place a 22 nf capacitor between this pin and creg1 to reduce vco noise.
adf7021 rev. a | page 18 of 64 05876-06 frequency offset (mhz) typical performance characteristics 0 phase noise (dbc/hz) ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ? 70 1 10 100 1000 10000 rf freq = 900mhz v dd = 2.3v temperature = 25c vco bias = 8 vco adjust = 3 i cp = 0.8ma i cp = 1.4ma i cp = 2.2ma figure 11. phase noise response at 900 mhz, v dd = 2.3 v ?40 ?36 ?32 ?28 ?24 ?20 ?16 ?12 ?8 ?4 0 4 8 12 16 rf output power (dbm) 0 4 8 12162024283236404448525660 05876-051 pa setting pa bias = 5a pa bias = 11a pa bias = 9a pa bias = 7a figure 12. rf output power vs. pa setting vbw 100hz 05876-05 start 300mhz res bw 100hz sweep 385.8ms (601pts) stop 3.5ghz 0 rf freq = 440mhz output power = 10dbm filter = t-stage lc filter marker = 52.2db 1r 1 figure 13. pa output harmonic response with t-stage lc filter 05876-047 center 869.5 25mhz res bw 300hz sweep 2.118s (601pts) span 50khz dr = 9.6kbps data = prbs9 f dev = 2.4khz rf freq = 869.5mhz vbw 300hz fsk gfsk figure 14. output spectrum in 2fsk and gfsk modes dr = 9.6kbps data = prbs9 f dev = 2.4khz rf freq = 869.5mhz 2fsk rc2fsk 05876-048 center 869.5 25mhz res bw 300hz sweep 2.118s (601pts) vbw 300hz span 50khz figure 15. output spectrum in 2fsk and raised cosine 2fsk modes vbw 300hz 05 res bw 300hz sweep 4.237s (601pts) sr = 4.8ksym/s data = prbs9 f dev = 2.4khz rf freq = 869.5mhz 876-049 center 869.493 8mhz span 100khz 4fsk rc4fsk figure 16. output spectrum in 4fsk and raised cosine 4fsk modes
adf7021 rev. a | page 19 of ref 15db m ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 ?130 ?128 ?126 ?124 ?122 ?120 ?118 ?116 ?114 ?112 ?110 ?108 64 05876-070 res bw 300hz center 869.5mhz vbw 300hz span 50hz sweep2.226s (401pts) samp log 10db/ atten 25db v avg 100 v1 v2 s3 fc dr = 9.6kbps data = prs9 f dev = 2.4khz rf freq = 869.5mhz 3fsk rc3fsk figure 17. output spectrum in 3fsk and raised cosine 3fsk modes 05876-06 frequency offset (khz) 8 output power (dbm) 0 ?10 10 ?20 ?30 ?40 ?100 ?50 50 0 100 ?50 ?60 ramp rate: cw only 256 codes/bit 128 codes/bit 64 codes/bit 32 codes/bit trace = max hold pa on/off rate = 3hz pa on/off cycles = 10000 v dd = 3.0v ?8 ?122 ?120 ?118 ?116 ?114 ?112 ?110 ?108 ?106 ?104 figure 18. output spect rum in maximum hold for various pa ramp rate options ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 3.0v, +25c 3.6v, ?40c 2.3v, +85c log ber 05876-052 rf input power (dbm) data rate = 9.6kbps f dev = 4khz rf freq = 868mhz if bw = 25khz figure 19. 2fsk sensitivity vs. v dd and temperature, f rf = 868 mhz 3.6v, ?40c 3.0v, +25c 2.3v, +85c 05876-053 rf input power (dbm) log ber data rate = 1kbps f dev = 1khz rf freq = 135mhz if bw = 12.5khz figure 20. 2fsk sensitivity vs. v dd and temperature, f rf = 135 mhz ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 ?120 ?115 ?110 ?105 ?100 ?95 0 5876-065 rf input power (dbm) log ber 2.3v +25c 3.0v +25c 3.6v +25c 2.3v ?40c 3.0v ?40c 3.6v ?40c 2.3v +85c 3.0v +85c 3.6v +85c 3fsk modulation data rate = 9.6kbps f dev = 2.4khz mod index = 0.5 rf freq = 440 mhz figure 21. 3fsk sensitivity vs. v dd and temperature, f rf = 440 mhz ?8 ?120 ?115 ?110 ?105 ?100 ?95 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 0 5876-066 rf input power (dbm) log ber data rate = 19.6kbps symbol rate = 9.8ksym/s f dev (inner) = 2.4khz mod index = 0.5 rf freq = 420mhz if bw = 12.5khz 2.3v +25c 3.0v +25c 3.6v +25c 2.3v ?40c 3.0v ?40c 3.6v ?40c 2.3v +85c 3.0v +85c 3.6v +85c figure 22. 4fsk sensitivity vs. v dd and temperature, f rf = 420 mhz
adf7021 rev. a | page 20 of 059 64 05876- frequency offset (mhz) blocking (db) ?10 0 10 20 30 40 50 60 70 80 90 ? ?22 ?18 ?14 ?10 ?6 ?2 0 2 6 10 14 18 22 05876-058 modulation index sensitivity point (dbm) rf freq = 868mhz wanted signal (10db above sensitivity point) = 2fsk, f dev = 4khz, data rate = 9.8kbps blocker = 2fsk, f dev = 4khz, data rate = 9.8kbps v dd = 3.0v temperature = 25c ?140 figure 23. wideband interference rejection ?120 ?100 ?80 ?60 ?40 ? 20 ?122.5 ?112.5 ?102.5 ?92.5 ?82.5 ?72.5 ?62.5 ?52.5 ?42.5 actual rf input level 05876-05 rf input (dbm) 5 rssi level (dbm) rssi readback level figure 24. digital rssi readback linearity ?10 429.80 429.85 429.90 429.95 430.00 430.05 430.10 430.15 430.20 0 10 20 30 40 50 60 70 rf freq = 430mhz external vco inductor data rate = 9.6kbps temperature = 25c, v dd = 3.0v blocking (db) 05876-054 rf frequency (mhz) calibrated uncalibrated figure 25. image rejection, uncalibrated vs. calibrated ?118 ?116 ?114 ?112 ?110 ?108 ?106 ?104 ?102 100 0 0.2 0.4 0.6 0.8 1.0 1.2 rf freq = 860mhz 2fsk modulation data rate = 9.6kbps if bw = 25khz v dd = 3.0v temperature = 25c discriminator bandwidth = 1 fsk frequency deviation discriminator bandwidth = 2 fsk frequency deviation figure 26. 2fsk sensitivity vs. modulation index vs. correlator discriminator bandwidth ?120 ?118 ?116 ?114 ?112 ?110 ?108 ?106 ?104 ?102 ?100 3fsk modulation v dd = 3.0v, temp = 25c data rate = 9.6kbps f dev = 2.4khz rf freq = 868mhz if bw = 18.75khz 05876-062 input power (dbm) log ber ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 viterbi detection threshold detection typically 3db figure 27. 3fsk receiver sensitivity using viterbi detection and threshold detection receiver symbol level +1 +3 ?1 ?3 0 05876-064 rf i/p level = ?70dbm data rate = 9.7kbps f dev (inner) = 1.2khz if bw = 25khz post demod bw = 12.4khz 22452 acqs m 50s figure 28. 4fsk receiver eye diagram measure using the test dac output
adf7021 rev. a | page 21 of 64 +1 ?1 0 05876-063 ? 70 4 20834 acqs m 20s c13 1.7v rf i/p level = ?70dbm data rate = 10kbps f dev = 2.5khz if bw = 12.5khz post demod bw = 12.4khz receiver symbol level figure 29. 3fsk receiver eye diagram measured using the test dac output 05876-069 lna gain, filter gain sensitivity (dbm) ?130 ?120 ?110 ?100 ?90 ?80 3, 72 (low gain mode) 10, 72 (medium gain mode) 30, 72 (high gain mode) high mixer linearity default mixer linearity modulation = 2fsk data rate = 9.6kbps f dev = 4khz if bw = 12.5khz demod = correlator sensitivity @ 1e-3 ber ip3 = ?3dbm ip3= ?5dbm ip3 = ?9dbm ip3 = ?20dbm ip3 = ?13.5dbm ip3 = ?24dbm figure 30. receive sensitivity vs. lna/if filter gain and mixer linearity settings (the input ip3 at each setting is also shown)
adf7021 rev. a | page 22 of 64 frequency synthesizer reference input the on-board crystal oscillator circuitry (see figure 31 ) can use a quartz crystal as the pll reference. using a quartz crystal with a frequency tolerance of 10 ppm for narrow-band appli- cations is recommended. it is possible to use a quartz crystal with >10 ppm tolerance, but to comply with the absolute frequency error specifications of narrow-band regulations (for example, arib std-t67 and etsi en 300-220), compen- sation for the frequency error of the crystal is necessary. the oscillator circuit is enabled by setting r1_db12 high. it is enabled by default on power-up and is disabled by bringing ce low. errors in the crystal can be corrected by using the automatic frequency control feature or by adjusting the fractional-n value (see the n counter section). osc1 osc2 cp1 cp2 05876-083 figure 31. oscillator circuit on the adf7021 two parallel resonant capacitors are required for oscillation at the correct frequency. their values are dependent upon the crystal specification. they should be chosen to make sure that the series value of capacitance added to the pcb track capacitance adds up to the specified load capacitance of the crystal, usually 12 pf to 20 pf. track capacitance values vary from 2 pf to 5 pf, depending on board layout. when possible, choose capacitors that have a very low temperature coefficient to ensure stable frequency operation over all conditions. using a tcxo reference a single-ended reference (tcxo, vcxo, or ocxo) can also be used with the adf7021. this is recommended for applications having absolute frequency accuracy requirements of <10 ppm, such as arib std-t67 or etsi en 300-220. there are two options for interfacing the adf7021 to an external reference oscillator. ? an oscillator with cmos output levels can be applied to osc2. the internal oscillator circuit should be disabled by setting r1_db12 low. ? an oscillator with 0.8 v p-p levels can be ac-coupled through a 22 pf capacitor into osc1. the internal oscillator circuit should be enabled by setting r1_db12 high. programmable crystal bias current bias current in the oscillator circuit can be configured between 20 a and 35 a by writing to the xtal_bias bits (r1_db[13:14]). increasing the bias current allows the crystal oscillator to power up faster. clkout divider and buffer the clkout circuit takes the reference clock signal from the oscillator section, shown in figure 31 , and supplies a divided- down, 50:50 mark-space signal to the clkout pin. the clkout signal is inverted with respect to the reference clock. an even divide from 2 to 30 is available. this divide number is set in r1_db[7:10]. on power-up, the clkout defaults to divide-by-8. dv dd clkout enable bit clkout osc1 divider 1to 15 2 05876-008 figure 32. clkout stage to disable clkout, set the divide number to 0. the output buffer can drive up to a 20 pf load with a 10% rise time at 4.8 mhz. faster edges can result in some spurious feedthrough to the output. a series resistor (1 k) can be used to slow the clock edges to reduce these spurs at the clkout frequency. r counter the 3-bit r counter divides the reference input frequency by an integer of 1 to 7. the divided-down signal is presented as the reference clock to the phase frequency detector (pfd). the divide ratio is set in r1_db[4:6]. maximizing the pfd frequency reduces the n value. this reduces the noise multiplied at a rate of 20 log(n) to the output and reduces occurrences of spurious components. register 1 defaults to r = 1 on power-up. pfd [hz] = xtal / r loop filter the loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the vco to the desired frequency. it also attenuates spurious levels generated by the pll. a typical loop filter design is shown in figure 33 . charge pump out vco 05876-010 figure 33. typical loop filter configuration the loop should be designed so that the loop bandwidth (lbw) is approximately 100 khz. this provides a good compromise between in-band phase noise and out-of-band spurious rejection. widening the lbw excessively reduces the time spent jumping between frequencies, but it can cause insufficient spurious attenua- tion. narrow-loop bandwidths can result in the loop taking long periods to attain lock and can also result in a higher level of power falling into the adjacent channel. the loop filter design on the eval-adf7021dbx should be used for optimum performance.
adf7021 rev. a | page 23 of 64 the free design tool adisimpll can also be used to design loop filters for the adf7021 (go to www.analog.com/adisimpll for details). n counter the feedback divider in the adf7021 pll consists of an 8-bit integer counter (r0_db[19:26]) and a 15-bit - fractional_n divider (r0_db[4:18]). the integer counter is the standard pulse-swallow type that is common in plls. this sets the minimum integer divide value to 23. the fractional divide value provides very fine resolution at the output, where the output frequency of the pll is calculated as ? ? ? ? 15 2 r out ? ? ? ? + = _ _ n fractional ninteger xtal f when rf_divide_by_2 (see the voltage controlled oscillator (vco) section) is selected, this formula becomes ? ? ? ? ? ? + = 15 2 _ 0.5 n fractional integer_n r xtal f out [] the combination of the integer_n (maximum = 255) and the fractional_n (maximum = 32,768/32,768) give a maximum n divider of 255 + 1. therefore, the minimum usable pfd is () 1255 + min hz = frequency output required maximum pfd for example, when operating in the european 868 mhz to 870 mhz band, pfd min equals 3.4 mhz. vco 4\n third-order - ? modulator pfd/ charge pump 4\r integer-n fractional-n 05876-011 05876-009 reference in figure 34. fractional-n pll voltage regulators the adf7021 contains four regulators to supply stable voltages to the part. the nominal regulator voltage is 2.3 v. regulator 1 requires a 3.9 resistor and a 100 nf capacitor in series between creg1 and gnd, whereas the other regulators require a 100 nf capacitor connected between cregx and gnd. when ce is high, the regulators and other associated circuitry are powered on, drawing a total supply current of 2 ma. bringing the ce pin low disables the regulators, reduces the supply current to less than 1 a, and erases all values held in the registers. the serial interface operates from a regulator supply. therefore, to write to the part, the user must have ce high and the regulator voltage must be stabilized. regulator status (creg4) can be monitored using the regulator_ready signal from muxout. muxout the muxout pin allows access to various digital points in the adf7021. the state of muxout is controlled by r0_db[29:31]. regulator_ready regulator_ready is the default setting on muxout after the transceiver is powered up. the power-up time of the regulator is typically 50 s. because the serial interface is powered from the regulator, the regulator must be at its nominal voltage before the adf7021 can be programmed. the status of the regulator can be monitored at muxout. when the regulator ready signal on muxout is high, programming of the adf7021 can begin. regulator_ready (default) digital_lock_detect rssi_ready tx_rx logic_zero tristate mux control dgnd d v dd muxout filter_cal_complete logic_one figure 35. muxout circuit filter_cal_complete muxout can be set to filter_cal_complete. this signal goes low for the duration of both a coarse if filter calibration and a fine if filter calibration. it can be used as an interrupt to a microcontroller to signal the end of the if filter calibration. digital_lock_detect digital_lock_detect indicates when the pll has locked. the lock detect circuit is located at the pfd. when the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. lock detect remains high until a 25 ns phase error is detected at the pfd. rssi_ready muxout can be set to rssi_ready. this indicates that the internal analog rssi has settled and a digital rssi readback can be performed. tx_rx tx_rx signifies whether the adf7021 is in transmit or receive mode. when in transmit mode, this signal is low. when in receive mode, this signal is high. it can be used to control an external tx/rx switch.
adf7021 rev. a | page 24 of 64 voltage controlled oscillator (vco) the adf7021 contains two vco cores. the first vco, the internal inductor vco, uses an internal lc tank and supports 862 mhz to 950 mhz and 431 mhz to 475 mhz operating bands. the second vco, the external inductor vco, uses an external inductor as part of its lc tank and supports the rf operating band of 80 mhz to 650 mhz. to minimize spurious emissions, both vcos operate at twice the rf frequency. the vco signal is then divided by 2 inside the synthesizer loop, giving the required frequency for the transmitter and the required local oscillator (lo) frequency for the receiver. a further divide-by-2 (rf_divide_by_2) is performed outside the synthesizer loop to allow operation in the 431 mhz to 475 mhz band (internal inductor vco) and 80 mhz to 325 mhz band (external inductor vco). the vco needs an external 22 nf capacitor between the cvco pin and the regulator (creg1) to reduce internal noise. vco loop filter vco bias r1_db(19:22) 220f cvco pin 05876-012 divide-by-2 r1_db18 2 2 mux to n divider to pa figure 36. voltage controlled oscillator (vco) internal inductor vco to select the internal inductor vco, set r1_db25 to logic 0, which is the default setting. vco bias current can be adjusted using r1_db[19:22]. to ensure vco oscillation, the minimum bias current setting under all conditions when using the internal inductor vco is 0x8. the vco should be re-centered, depending on the required frequency of operation, by programming the vco_adjust bits (r1_db[23:24]). this is detailed in tabl e 9 . external inductor vco when using the external inductor vco, the center frequency of the vco is set by the internal varactor capacitance and the combined inductance of the external chip inductor, bond wire, and pcb track. the external inductor is connected between the l2 and l1 pins. a plot of the vco operating frequency vs. total external inductance (chip inductor + pcb track) is shown in figure 37 . 750 05876-061 0 5 10 15 20 25 30 200 250 300 350 400 450 500 550 600 650 700 total external inductance (nh) frequency (mhz) f max (mhz) f min (mhz) figure 37. direct rf output vs. total external inductance the inductance for a pcb track using fr4 material is approxi- mately 0.57 nh/mm. this should be subtracted from the total value to determine the correct chip inductor value. typically, a particular inductor value allows the adf7021 to function over a range of 6% of the rf operating frequency. when the rf_divide_by_2 bit (r1_db18) is selected, this range becomes 3%. at 400 mhz, for example, an operating range of 24 mhz (that is, 376 mhz to 424 mhz) with a single inductor (vco range centered at 400 mhz) can be expected. the vco tuning voltage can be checked for a particular rf output frequency by measuring the voltage on the vcoin pin when the part is fully powered up in transmit or receive mode. the vco tuning range is 0.2 v to 2 v. the external inductor value should be chosen to ensure that the vco is operating as close as possible to the center of this tuning range. this is particularly important for rf frequencies <200 mhz, where the vco gain is reduced and a tuning range of <6 mhz exists. the vco operating frequency range can be adjusted by programming the vco_adjust bits (r1_db[23:24]). this typically allows the vco operating range to be shifted up or down by a maximum of 1% of the rf frequency. to select the external inductor vco, set r1_db25 to logic 1. the vco_bias_current should be set depending on the frequency of operation (as indicated in table 9 ). table 9. rf output frequency ranges for internal and external inductor vcos and required register settings rf frequency output (mhz) vco to be used rf divide by 2 register settings (vco_inductor) r1_db25 (rf_divide_by_2) r1_db18 (vco_adjust) r1_db[23:24] (vco_bias) r1_db[19:22] 900 to 950 internal l no 0 0 11 8 862 to 900 internal l no 0 0 00 8 450 to 470 internal l yes 0 1 11 8 431 to 450 internal l yes 0 1 00 8 450 to 650 external l no 1 0 xx 4 200 to 450 external l no 1 0 xx 3 80 to 200 external l yes 1 1 xx 2
adf7021 rev. a | page 25 of 64 choosing channels for best system performance an interaction between the rf vco frequency and the reference frequency can lead to fractional spur creation. when the synthesizer is in fractional mode (that is, the rf vco and reference frequencies are not integer related), spurs can appear on the vco output spectrum at an offset frequency that corresponds to the difference frequency between an integer multiple of the reference and the vco frequency. these spurs are attenuated by the loop filter. they are more noticeable on channels close to integer multiples of the reference where the difference frequency may be inside the loop bandwidth; thus, the name integer boundary spurs. the occurrence of these spurs is rare because the integer frequencies are around multiples of the reference, which is typically >10 mhz. to avoid having very small or very large values in the fractional register, choose a suitable reference frequency.
adf7021 rev. a | page 26 of 64 transmitter rf output stage 3 4 ... 8 ... 1 6 data bits pa ramp 0 (no ramp) pa ramp 1 (256 codes per bit) pa ramp 2 (128 codes per bit) pa ramp 3 (64 codes per bit) pa ramp 4 (32 codes per bit) pa ramp 5 (16 codes per bit) pa ramp 6 (8 codes per bit) pa ramp 7 (4 codes per bit) 1 2 the power amplifier (pa) of the adf7021 is based on a single- ended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dbm into a 50 load at a maximum frequency of 950 mhz. the pa output current and consequently, the output power, are programmable over a wide range. the pa configuration is shown in figure 38 . the output power is set using r2_db[13:18]. 0 5876-0 13 idac 2 6 r2_db(13:18) r2_db7 r2_db(11:12) + rfgnd rfout 05876-014 05876-015 from vco r0_db27 figure 38. pa configuration the pa is equipped with overvoltage protection, which makes it robust in severe mismatch conditions. depending on the appli- cation, users can design a matching network for the pa to exhibit optimum efficiency at the desired radiated output power level for a wide range of antennas, such as loop or monopole antennas. see the lna/pa matching section for more information. pa ramping when the pa is switched on or off quickly, its changing input impedance momentarily disturbs the vco output frequency. this process is called vco pulling, and it manifests as spectral splatter or spurs in the output spectrum around the desired carrier frequency. some radio emissions regulations place limits on these pa transient-induced spurs (for example, etsi en 300 220). by gradually ramping the pa on and off, pa transient spurs are minimized. the adf7021 has built-in pa ramping configurability. as figure 39 illustrates, there are eight ramp rate settings, defined as a certain number of pa setting codes per one data bit period. the pa steps through each of its 64 code levels but at different speeds for each setting. the ramp rate is set by configuring r2_db[8:10]. if the pa is enabled/disabled by pa_enable (r2_db7), it ramps up at the programmed rate but turns off hard. if the pa is enabled/disabled by tx/rx (r0_db27), it ramps up and down at the programmed rate. figure 39. pa ramping settings pa bias currents the pa_bias bits (r2_db[11:12]) facilitate an adjustment of the pa bias current to further extend the output power control range, if necessary. if this feature is not required, the default value of 9 a is recommended. if output power of greater than 10 dbm is required, a pa bias setting of 11 a is recommended. the output stage is powered down by resetting r2_db7. modulation schemes the adf7021 supports 2fsk, 3fsk, and 4fsk modulation. the implementation of these modulation schemes is shown in figure 40 . to pa stage vco n third-order - modulator pfd/ charge pump ref integer-n f_deviation 1 ? d 2 pr shaping 4fsk bit symbol mapper mux txdata 2fsk 4fsk gaussian or raised cosine filtering pre- coder loop filter frac_n 2 3fsk figure 40. transmit modulation implementation
adf7021 rev. a | page 27 of 64 setting the transmit data rate in all modulation modes except oversampled 2fsk mode, an accurate clock is provided on the txrxclk pin to latch the data from the microcontroller into the transmit section at the required data rate. the exact frequency of this clock is defined by data clk = 32 __ __ divide clkcdr divide clk demod xtal where: xtal is the crystal or tcxo frequency. demod_clk_divide is the divider that sets the demodulator clock rate (r3_db[6:9]). cdr_clk_divide is the divider that sets the cdr clock rate (r3_db[10:17]). refer to the register 3transmit/receive clock register section for more programming information. setting the fsk transmit deviation frequency in all modulation modes, the deviation from the center frequency is set using the tx_frequency_deviation bits (r2_db[19:27]). the deviation from the center frequency in hz is as follows: for direct rf output, f dev [hz] = 16 2 _ _ deviation frequency txpfd for rf_divide_by_2 enabled, f dev [hz] = 16 2 _ _ 5. deviation frequency txpfd 0 where tx_frequency_deviation is a number from 1 to 511 (r2_db[19:27]). in 4fsk modulation, the four symbols (00, 01, 11, 10) are transmitted as 3 f dev and 1 f dev . binary frequency shift keying (2fsk) two-level frequency shift keying is implemented by setting the n value for the center frequency and then toggling it with the txdata line. the deviation from the center frequency is set using the tx_frequency_deviation bits, r2_db[19:27]. 2fsk is selected by setting the modulation_scheme bits (r2_db[4:6]) to 000. minimum shift keying (msk) or gaussian minimum shift keying (gmsk) is supported by selecting 2fsk modulation and using a modulation index of 0.5. a modulation index of 0.5 is set up by configuring r2_db[19:27] for a freq deviation = 0.25 transmit data rate. 3-level frequency sh ift keying (3fsk) in 3-level fsk modulation (also known as modified duobinary fsk), the binary data (logic 0 and logic 1) is mapped onto three distinct frequencies, the carrier frequency (f c ), the carrier frequency minus a deviation frequency (f c ? f dev ), and the carrier frequency plus the deviation frequency (f c + f dev ). a logic 0 is mapped to the carrier frequency while a logic 1 is either mapped onto frequency f c ? f dev or f c + f dev . f c f c ? f dev f c + f dev rf frequency 0 +1 ?1 05876-057 figure 41. 3fsk symbol -to-frequency mapping compared to 2fsk, this bits-to-frequency mapping results in a reduced transmission bandwidth because some energy is removed from the rf sidebands and transferred to the carrier frequency. at low modulation index, 3fsk improves the transmit spectral efficiency by up to 25% when compared to 2fsk. bit-to-symbol mapping for 3fsk is implemented using a linear convolutional encoder that also permits viterbi detection to be used in the receiver. a block diagram of the transmit hardware used to realize this system is shown in figure 42 . the convolu- tional encoder polynomial used to implement the transmit spectral shaping is p(d) = 1 ? d 2 where: p is the convolutional encoder polynomial. d is the unit delay operator. a digital precoder with transfer function 1/p(d) implements an inverse modulo-2 operation of the 1 ? d 2 shaping filter in the transmitter. convolutional encoder p(d) precoder 1/p(d) fsk mod control and data filtering tx data 05876-046 0, 1 0, +1, ?1 0, 1 to n divider f c f c + f dev f c ? f dev figure 42. 3fsk encoding the signal mapping of the input binary transmit data to the 3-level convolutional output is shown in table 10 . the convolutional encoder restricts the maximum number of sequential +1s or ?1s to two and delivers an equal number of +1s and ?1s to the fsk modulator, thus ensuring equal spectral energy in both rf sidebands.
adf7021 rev. a | page 28 of 64 table 10. 3-level signal mapping of the convolutional encoder txdata 1 0 1 1 0 0 1 0 0 1 precoder output 1 0 0 1 0 1 1 1 1 0 encoder output +1 0 ?1 +1 0 0 +1 0 0 ?1 another property of this encoding scheme is that the transmitted symbol sequence is dc-free, which facilitates symbol detection and frequency measurement in the receiver. in addition, there is no code rate loss associated with this 3-level convolutional encoder; that is, the transmitted symbol rate is equal to the data rate presented at the transmit data input. 3fsk is selected by setting the modulation_scheme bits (r2_db[4:6]) to 010. it can also be used with raised cosine filtering to further increase the spectral efficiency of the transmit signal. 4-level frequency sh ift keying (4fsk) in 4fsk modulation, two bits per symbol spectral efficiency is realized by mapping consecutive input bit-pairs in the tx data bit stream to one of four possible symbols (?3, ?1, +1, +3). thus, the transmitted symbol rate is half of the input bit rate. by minimizing the separation between symbol frequencies, 4fsk can have high spectral efficiency. the bit-to-symbol mapping for 4fsk is gray coded and is shown in figure 43 . tx data symbol frequencies f +3 f dev + f dev ? f dev 00011011 t ?3 f dev 05876-016 figure 43. 4fsk bit-to-symbol mapping the inner deviation frequencies (+f dev and ? f dev ) are set using the tx_frequency_deviation bits, r2_db[19:27]. the outer deviation frequencies are automatically set to three times the inner deviation frequency. the transmit clock from pin txrxclk is available after writing to register 3 in the power-up sequence for receive mode. the msb of the first symbol should be clocked into the adf7021 on the first transmit clock pulse from the adf7021 after writing to register 3. refer to figure 6 for more timing information. oversampled 2fsk in oversampled 2fsk, there is no data clock from the txrxclk pin. instead, the transmit data at the txrxdata pin is sampled at 32 times the programmed rate. this is the only modulation mode that can be used with the uart mode interface for data transmission (refer to the interfacing to microcontroller/dsp section for more information). spectral shaping gaussian or raised cosine filtering can be used to improve transmit spectral efficiency. the adf7021 supports gaussian filtering (bandwidth time [bt] = 0.5) on 2fsk modulation. raised cosine filtering can be used with 2fsk, 3fsk, or 4fsk modulation. the roll off factor (alpha) of the raised cosine filter has programmable options of 0.5 and 0.7. both the gaussian and raised cosine filters are implemented using linear phase digital filter architectures that deliver precise control over the bt and alpha filter parameters, and guarantee a transmit spectrum that is very stable over temperature and supply variation. gaussian frequency shift keying (gfsk) gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the transmit data. the bt product of the gaussian filter used is 0.5. gaussian filtering can only be used with 2fsk modulation. this is selected by setting r2_db[4:6] to 001. raised cosine filtering raised cosine filtering provides digital prefiltering of the transmit data by using a raised cosine filter with a roll-off factor (alpha) of either 0.5 or 0.7. the alpha is set to 0.5 by default, but the raised cosine filter bandwidth can be increased to provide less aggressive data filtering by using an alpha of 0.7 (set r2_db30 to logic 1). raised cosine filtering can be used with 2fsk, 3fsk, and 4fsk. raised cosine filtering is enabled by setting r2_db[4:6] as outlined in table 11 .
adf7021 rev. a | page 29 of 64 modulation and filtering options the various modulation and data filtering options are described in table 11 . table 11. modulation and filtering options modulation data filtering r2_db[4:6] binary fsk 2fsk none 000 msk 1 none 000 oqpsk with half sine baseband shaping 2 none 000 gfsk gaussian 001 gmsk 3 gaussian 001 rc2fsk raised cosine 101 oversampled 2fsk none 100 3-level fsk 3fsk none 010 rc3fsk raised cosine 110 4-level fsk 4fsk none 011 rc4fsk raised cosine 111 1 msk is 2fsk modulation with a modulation index = 0.5. 2 offset quadrature phase shift keying (oqpsk) with half sine baseband shaping is spectrally equivalent to msk. 3 gmsk is gfsk with a modulation index = 0.5. transmit latency transmit latency is the delay time from the sampling of a bit/symbol by the txrxclk signal to when that bit/symbol appears at the rf output. the latency without any data filtering is 1 bit. the addition of data filtering adds a further latency as outlined in tabl e 12 . it is important that the adf7021 be left in transmit mode after the last data bit is sampled by the data clock to account for this latency. the adf7021 should stay in transmit mode for a time equal to the number of latency bit periods for the applied modulation scheme. this ensures that all of the data sampled by the txrxclk signal appears at rf. the figures for latency in table 12 assume that the positive txrxclk edge is used to sample data (default). if the txrxclk is inverted by setting r2_db[28:29], an additional 0.5 bit latency can be added to all values in table 12 . table 12. bit/symbol latency in transmit mode for various modulation schemes modulation latency 2fsk 1 bit gfsk 4 bits rc2fsk, alpha = 0.5 5 bits rc2fsk, alpha = 0.7 4 bits 3fsk 1 bit rc3fsk, alpha = 0.5 5 bits rc3fsk, alpha = 0.7 4 bits 4fsk 1 symbol rc4fsk, alpha = 0.5 5 symbols rc4fsk, alpha = 0.7 4 symbols test pattern generator the adf7021 has a number of built-in test pattern generators that can be used to facilitate radi o link setup or rf measurement. a full list of the supported patterns is shown in table 13 . the data rate for these test patterns is the programmed data rate set in register 3. the pn9 sequence is suitable for test modulation when carrying out adjacent channel power (acp) or occupied bandwidth measurements. table 13. transmit test pattern generator options test pattern r15_db[8:10] normal 000 transmit carrier 001 transmit + f dev tone 010 transmit ? f dev tone 011 transmit 1010 pattern 100 transmit pn9 sequence 101 transmit swd pattern repeatedly 110
adf7021 rev. a | page 30 of 64 receiver section rf front end the adf7021 is based on a fully integrated, low if receiver architecture. the low if architecture facilitates a very low external component count and does not suffer from powerline- induced interference problems. figure 44 shows the structure of the receiver front end. the many programming options allow users to trade off sensitivity, linearity, and current consumption to best suit their application. to achieve a high level of resilience against spurious reception, the low noise amplifier (lna) features a differential input. switch sw2 shorts the lna input when transmit mode is selected (r0_db27 = 0). this feature facilitates the design of a combined lna/pa matching network, avoiding the need for an external rx/tx switch. see the lna/pa matching section for details on the design of the matching network. sw2 lna rfin rfinb t x/rx select (r0_db27) lna mode (r9_db25) lna current (r9_db[26:27]) mixer linearity (r9_db28) lo i (to filter) q (to filter) lna gain (r9_db[20:21]) 017 lna/mixer enable (r8_db6) 05876- figure 44. rf front end the lna is followed by a quadrature downconversion mixer, which converts the rf signal to the if frequency of 100 khz. an important consideration is that the output frequency of the synthesizer must be programmed to a value 100 khz below the center frequency of the received channel. the lna has two basic operating modes: high gain/low noise mode and low gain/low power mode. to switch between these two modes, use the lna_mode bit (r9_db25). the mixer is also configurable between a low current and an enhanced linearity mode using the mixer_linearity bit (r9_db28). based on the specific sensitivity and linearity requirements of the application, it is recommended to adjust the lna_mode bit and mixer_linearity bit as outlined in table 14 . the gain of the lna is configured by the lna_gain bits (r9_db[20:21]) and can be set by either the user or the automatic gain control (agc) logic. if filter if filter settings out-of-band interference is rejected by means of a fifth-order butterworth polyphase if filter centered on a frequency of 100 khz. the bandwidth of the if filter can be programmed to 12.5 khz, 18.75 khz, or 25 khz by r4_db[30:31] and should be chosen as a compromise between interference rejection and attenuation of the desired signal. if the agc loop is disabled, the gain of the if filter can be set to one of three levels by using the filter_gain bits (r9_db[22:23]). the filter gain is adjusted automatically if the agc loop is enabled. if filter bandwidth and center frequency calibration to compensate for manufacturing tolerances, the if filter should be calibrated after power-up to ensure that the bandwidth and center frequency are correct. coarse and fine calibration schemes are provided to offer a choice between fast calibration (coarse calibration) and high filter centering accuracy (fine calibration). coarse calibration is enabled by setting r5_db4 high. fine calibration is enabled by setting r6_db4 high. for details on when it is necessary to perform a filter calibration, and in what applications to use either a coarse calibration or fine calibration, refer to the if filter bandwidth calibration section. it is necessary to do a coarse calibration before doing a fine calibration. if the if_fine_cal bit (r6_db4) has already been configured high, it is possible to do a fine calibration by writing only to register 5 . once initiated by writing to the part, the cali- bration is performed automatically without any user intervention. calibration time is 200 s for coarse calibration and a few milliseconds for fine calibration, during which time the adf7021 should not be accessed. the if filter calibration logic requires that the if_filter_divider bits (r5_db[5:13]) be set such that khz50 __ [hz] = divider filterif xtal if filter fine calibration overview the fine calibration uses two internally generated tones at certain offsets around the if filter. the two tones are attenuated by the if filter, and the level of this attenuation is measured using the rssi. the filter center frequency is adjusted to allow equal attenuation of both tones. the attenuation of the two test tones is then remeasured. this continues for a maximum of 10 rssi measurements, at which stage the calibration algorithm sets the if filter center frequency to within 0.5 khz of 100 khz. t he frequency of these tones is set by the following bits: ? if_cal_lower_tone_divider (r6_db[5:12]) ? if_cal_upper_tone_divider (r6_db[13:20]) it is recommended to place the lower and upper tones as close as possible to 65.8 khz and 131.5 khz, respectively, as outlined in the following equations: khz8.65 2 ____ = divide tone lower calif xtal khz5.131 2 ____ = divide tone upper calif xtal
adf7021 rev. a | page 31 of 64 the calibration algori thm adjusts the filter center frequency and measures the rssi 10 times during the calibration. the time for an adjustment plus rssi measurement is given by clkseq ll_time if_cal_dwe timencalibratio toneif = 05876-018 it is recommended that the if tone calibration time be at least 500 s. the total time for the if filter fine calibration is given by if filter fine calibration time = if tone calibration time 10 rssi/agc the rssi is implemented as a successive compression log amp following the baseband (bb) channel filtering. the log amp achieves 3 db log linearity. it also doubles as a limiter to convert the signal-to-digital levels for the fsk demodulator. the offset correction circuit uses the bbos_clk_divide bits (r3_db[4:5]), which should be set between 1 mhz and 2 mhz. the rssi level is converted for user readback and for digitally controlled agc by an 80-level (7-bit) flash adc. this level can be converted to input power in dbm. by default, the agc is on when powered up in receive mode. 1 ifwr ifwr ifwr ifwr latch aaa offset correction r clk adc rssi fsk demod figure 45. rssi block diagram rssi thresholds when the rssi is above agc_high_threshold (r9_db[11:17]), the gain is reduced. when the rssi is below agc_low_threshold (r9_db[4:10]), the gain is increased. the thresholds default to 30 and 70 on power-up in receive mode. a delay (set by agc_clock_divide, r3_db[26:31]) is programmed to allow for settling of the loop. a value of 10 is recommended. the user has the option of changing the two threshold values from the defaults of 30 and 70 (register 9). the default agc setup values should be adequate for most applications. the threshold values must be chosen to be more than 30 apart for the agc to operate correctly. offset correction clock in register 3 , the user should set the bbos_clk_divide bits (r3_db[4:5]) to give a baseband offset clock (bbos clk) frequency between 1 mhz and 2 mhz. bbos clk [hz] = xtal/(bbos_clk_divide) where bbos_clk_divide can be set to 4, 8, 16, or 32. agc information and timing agc is selected by default and operates by setting the appropriate lna and filter gain settings for the measured rssi level. it is possible to disable agc by writing to register 9 if the user wants to enter one of the modes listed in table 14 . the time for the agc circuit to settle and, therefore, the time it takes to measure the rssi accurately, is typically 300 s. however, this depends on how many gain settings the agc circuit has to cycle through. after each gain change, the agc loop waits for a programmed time to allow transients to settle. this agc update rate is set according to agc update rate [hz] = divide clkagc divide clkseq __ [hz] __ where: agc_clk_divide is set by r3_db[26:31]. a value of 10 is recommended. seq_clk_divide = 100 khz (r3_db[18:25]). by using the recommended setting for agc_clk_divide, the total agc settling time is [hz] [sec] rateupdate agc changes gainagcofnumber time settling agc = the worst case for agc settling is when the agc control loop has to cycle through all five gain settings, which gives a maximum agc settling time of 500 s. table 14. lna/mixer modes receiver mode lna_mode (r9_db25) lna_gain (r9_db[20:21]) mixer_linearity (r9_db28) sensitivity (2fsk, dr = 4.8 kbps, f dev = 4 khz) rx current consumption (ma) input ip3 (dbm) high sensitivity mode (default) 0 30 0 ?118 24.6 ?24 enhanced linearity high gain 0 30 1 ?114.5 24.6 ?20 medium gain 1 10 0 ?112 22.1 ?13.5 enhanced linearity medium gain 1 10 1 ?105.5 22.1 ?9 low gain 1 3 0 ?100 22.1 ?5 enhanced linearity low gain 1 3 1 ?92.3 22.1 ?3
adf7021 rev. a | page 32 of 64 rssi formula (converting to dbm) i q limiters the rssi formula is frequency correlator input power [dbm] = ?130 dbm + ( readback code + gain mode correction ) 0.5 where: readback code is given by bit rv7 to bit rv1 in the readback register (see the readback format section). gain mode correction is given by the values in table 15 . the lna gain (lg2, lg1) and filter gain (fg2, fg1) values are also obtained from the readback register, as part of an rssi readback. table 15. gain mode correction lna gain (lg2, lg1) filter gain (fg2, fg1) gain mode correction h (1, 0) h (1, 0) 0 m (0, 1) h (1, 0) 24 m (0, 1) m (0, 1) 38 m (0, 1) l (0, 0) 58 l (0, 0) l (0, 0) 86 an additional factor should be introduced to account for losses in the front-end-matching network/antenna. demodulation, detection, and cdr system overview an overview of the demodulation, detection, and clock and data recovery (cdr) of the received signal on the adf7021 is shown in figure 46 . the quadrature outputs of the if filter are first limited and then fed to either the correlator fsk demodulator or the linear fsk demodulator. the correlator demodulator is used to demodulate 2fsk, 3fsk, and 4fsk. the linear demodulator is used for frequency measurement and is enabled when the afc loop is active. the linear demodulator can also be used to demodulate 2fsk. following the demodulator, a digital post demodulator filter removes excess noise from the demodulator signal output. threshold/slicer detection is used for data recovery of 2fsk and 4fsk. data recovery of 3fsk can be implemented using either threshold detection or viterbi detection. an on-chip cdr pll is used to resynchronize the received bit stream to a local clock. it outputs the retimed data and clock on the txrxdata and txrxclk pins, respectively. post demod filter viterbi detection mux clock and data recovery txrxdata txrx clk linear demodulator mux 3fsk 05876-080 threshold detection 2/3/4fsk figure 46. overview of demodulation, detection, and cdr process correlator demodulator the correlator demodulator can be used for 2fsk, 3fsk, and 4fsk demodulation. figure 47 shows the operation of the correlator demodulator for 2fsk. if ? f dev if + f dev i if q limiters r4_db(10:19) r4_db7 dot/cross product frequency cor r elator discriminator bw r4_db9 rx data invert discrim bw 2fsk = +1, ?1 3fsk = +1, 0, ?1 4fsk = +3, +1, ?1, ?3 output levels: 05876-079 figure 47. 2fsk correlator demodulator operation the quadrature outputs of the if filter are first limited and then fed to a digital frequency correlator that performs filtering and frequency discrimination of the 2fsk/3fsk/4fsk spectrum. for 2fsk modulation, data is recovered by comparing the output levels from two correlators. the performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of additive white gaussian noise (awgn). this method of fsk demodulation provides approximately 3 db to 4 db better sensitivity than a linear demodulator.
adf7021 linear demodulator figure 48 shows a block diagram of the linear demodulator. rev. a | page 33 of 64 0 5876-073 post demod filter envelope detector slicer 2fsk frequency if level i q limiter linear discriminator r4_db(20:29) frequency readback and afc loop + 2fsk rx data rxclk figure 48. block diagram of linear fsk demodulator a digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs. the discriminator output is filtered and averaged using a combined averaging filter and envelope detector. the demodulated 2fsk data from the post demodulator filter is recovered by threshold detecting the envelope detector output, as shown in figure 48 . this method of demodulation corrects for frequency errors between transmitter and receiver when the received spectrum is close to or within the if bandwidth. this envelope detector output is also used for afc readback and provides the frequency estimate for the afc control loop. post demodulator filter a second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. the bandwidth of this post demodulator filter is programmable and must be optimized for the users data rate and received modulation type. if the bandwidth is set too narrow, performance degrades due to intersymbol interference (isi). if the bandwidth is set too wide, excess noise degrades the performance of the receiver. the post_demodulator_bw bits (r4_db[20:29]) set the bandwidth of this filter. 2fsk bit slicer/threshold detection 2fsk demodulation can be implemented using the correlator fsk demodulator or the linear fsk demodulator. in both cases, threshold detection is used for data recovery at the output of the post demodulation filter. the output signal levels of the correlator demodulator are always centered about zero. therefore, the slicer threshold level can be fixed at zero, and the demodulator performance is independent of the run-length constraints of the transmit data bit stream. this results in robust data recovery that does not suffer from the classic baseline wander problems that exist in the more traditional fsk demodulators. when the linear demodulator is used for 2fsk demodulation, the output of the envelope detector is used as the slicer threshold, and this output tracks frequency errors that are within the if filter bandwidth. 3fsk and 4fsk threshold detection 4fsk demodulation is implemented using the correlator demodulator followed by the post demodulator filter and threshold detection. the output of the post demodulation filter is a 4-level signal that represents the transmitted symbols (?3, ?1, +1, +3). threshold detection of 4fsk requires three threshold settings, one that is always fixed at 0 and two that are programmable and are symmetrically placed above and below 0 using the 3fsk/4fsk_slicer_threshold bits (r13_db[4:10]). 3fsk demodulation is implemented using the correlator demodu- lator, followed by a post demodulator filter. the output of the post demodulator filter is a 3-level signal that represents the transmitted symbols (?1, 0, +1). data recovery of 3fsk can be implemented using threshold detection or viterbi detection. threshold detection is implemented using two thresholds that are programmable and are symmetrically placed above and below zero using the 3fsk/4fsk_slicer_threshold bits (r13_db[4:10]). 3fsk viterbi detection viterbi detection of 3fsk operates on a four-state trellis and is implemented using two interleaved viterbi detectors operating at half the symbol rate. the viterbi detector is enabled by r13_db11. to facilitate different run length constraints in the transmitted bit stream, the viterbi path memory length is programmable in steps of 4 bits, 6 bits, 8 bits, or 32 bits by setting the viterbi_path_memory bits (r13_db[13:14]). this should be set equal to or longer than the maximum number of consecutive 0s in the interleaved transmit bit stream. when used with viterbi detection, the receiver sensitivity for 3fsk is typically +3 db better than that obtained using threshold detection. when the viterbi detector is enabled, however, the receiver bit latency is increased by twice the viterbi path memory length. clock recovery an oversampled digital clock and data recovery (cdr) pll is used to resynchronize the received bit stream to a local clock in all modulation modes. the oversampled clock rate of the pll (cdr clk) must be set at 32 times the symbol rate (see the register 3transmit/receive clock register section). the maximum data/symbol rate tolerance of the cdr pll is determined by the number of zero-crossing symbol transitions in the transmitted packet. for example, if using 2fsk with a 101010 preamble, a maximum tolerance of 3.0% of the data rate is achieved. however, this tolerance is reduced during recovery of the remainder of the packet where symbol transi- tions may not be guaranteed to occur at regular intervals. to maximize the data rate tolerance of the cdr, some form of encoding and/or data scrambling is recommended that guarantees a number of transitions at regular intervals. for
adf7021 rev. a | page 34 of 64 for 3fsk, example, using 2fsk with manchester-encoded data achieves a data rate tolerance of 2.0%. the cdr pll is designed for fast acquisition of the recovered symbols during preamble and typically achieves bit synchro- nization within 5-symbol transitions of preamble. in 4fsk modulation, the tolerance using the +3, ?3, +3, ?3 preamble is 3% of the symbol rate (or 1.5% of the data rate). however, this tolerance is reduced during recovery of the remainder of the packet where symbol transitions may not be guaranteed to occur at regular intervals. to maximize the symbol/data rate tolerance, the remainder of the 4fsk packet should be constructed so that the transmitted symbols retain close to dc-free properties by using data scrambling and/or by inserting specific dc balancing symbols that are inserted in the transmitted bit stream at regular intervals such as after every 8 or 16 symbols. in 3fsk modulation, the linear convolutional encoder scheme guarantees that the transmitted symbol sequence is dc-free, facilitating symbol detection. however, tx data scrambling is recommended to limit the run length of zero symbols in the transmit bit stream. using 3fsk, the cdr data rate tolerance is typically 0.5%. receiver setup correlator demodulator setup to enable the correlator for various modulation modes, refer to table 16 . table 16. enabling the correlator demodulator received modulation demod_scheme (r4_db[4:6]) 2fsk 001 3fsk 010 4fsk 011 to optimize receiver sensitivity, the correlator bandwidth must be optimized for the specific deviation frequency and modulation used by the transmitter. the discriminator bandwidth is controlled by r4_db[10:19] and is defined as ( ) 3 10400 _ = kclk demod bwtor discrimina where: demod clk is as defined in the register 3transmit/receive clock register section. k is set for each modulation mode according to the following: for 2fsk, ? ? ? ? ? ? ? ? = dev f roundk 3 10100 ? ? ? ? ? ? ? ? = dev f roundk 2 10100 3 for 4fsk, ? ? ? ? ? ? ? ? = dev fsk f roundk 4 10100 3 4 where: round is rounded to the nearest integer. round 4fsk is rounded to the nearest of the following integers: 32, 31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3. f dev is the transmit frequency deviation in hz. for 4fsk, f dev is the frequency deviation used for the 1 symbols (that is, the inner frequency deviations). to optimize the coefficients of the correlator, r4_db7 and r4_db[8:9] must also be assigned. the value of these bits depends on whether k is odd or even. these bits are assigned according to table 17 and table 18 . table 17. assignment of correlat or k value for 2fsk and 3fsk k k/2 (k + 1)/2 r4_db7 r4_db[8:9] even even n/a 0 00 even odd n/a 0 10 odd n/a even 1 00 odd n/a odd 1 10 table 18. assignment of correlator k value for 4fsk k r4_db7 r4_db[8:9] even 0 00 odd 1 00 linear demodu lator setup the linear demodulator can be used for 2fsk demodulation. to enable the linear demodulator, set the demod_scheme bits (r4_db[4:6]) to 000. post demodulator filter setup the 3 db bandwidth of the post demodulator filter should be set according to the received modulation type and data rate. the bandwidth is controlled by r4_db[20:29] and is given by clk demod f bw demod post cutoff = 2 __ 11 where f cutoff is the target 3 db bandwidth in hz of the post demodulator filter. table 19. post demodulator filter bandwidth settings for 2fsk/3fsk/4fsk modulation schemes received modulation post demodulator filter bandwidth, f cutoff (hz) 2fsk 0.75 data rate 3fsk 1 data rate 4fsk 1.6 symbol rate (= 0.8 data rate)
adf7021 rev. a | page 35 of 64 3fsk viterbi detector setup the viterbi detector can be used for 3fsk data detection. this is activated by setting r13_db11 to logic 1. the viterbi path memory length is programmable in steps of 4, 6, 8, or 32 bits (viterbi_path_memory, r13_db[13:14]). the path memory length should be set equal to or greater than the maximum number of consecutive 0s in the interleaved transmit bit stream. the viterbi detector also uses threshold levels to implement the maximum likelihood detection algorithm. these thresholds are programmable via the 3fsk/4fsk_slicer_threshold bits (r13_db[4:10]). these bits are assigned as follows: 3fsk/4fsk_slicer_threshold = ? ? ? ? ? ? ? ? 3 10100 75 k deviation requency transmit f where k is the value calculated for correlator discriminator bandwidth. 3fsk threshold detector setup to activate threshold detectio n of 3fsk, r13_db11 should be set to logic 0. the 3fsk/4fsk_slicer_threshold bits (r13_db[4:10]) should be set as outlined in the 3fsk viterbi detector setup section. 3fsk cdr setup in 3fsk, a transmit preamble of at least 40 bits of continuous 1s is recommended to ensure a maximum number of symbol transitions for the cdr to acquire lock. the clock and data recovery for 3fsk requires a number of parameters in register 13 to be set (see table 20 ). 4fsk threshold detector setup the threshold for the 4fsk detector is set using the 3fsk/4fsk_slicer_threshold bits (r13_db[4:10]). the threshold should be set according to 3fsk/4fsk_slicer_threshold = ? ? ? ? ? ? ? ? 3 10100 87 k deviation txouter4fsk where k is the value calculated for correlator discriminator bandwidth. table 20. 3fsk cdr settings parameter recommended setting purpose phase_correction (r13_db12) 1 phase correction on 3fsk_cdr_threshold (r13_db[15:21]) ? ? ? ? ? ? ? ? 3 10100 62 k deviation requency transmit f where k is the value calculated for correlator discriminator bandwidth. sets cdr decision threshold levels 3fsk_preamble_time_validate (r13_db [22:25]) 1111 preamble detector time qualifier
adf7021 rev. a | page 36 of 64 demodulator considerations 2fsk preamble the recommended preamble bit pattern for 2fsk is a dc-free pattern (such as a 10101010 pattern). preamble patterns with longer run-length constraints (such as 11001100) can also be used but result in a longer synchronization time of the received bit stream in the receiver. the preamble needs to allow enough bits for agc settling of the receiver and cdr acquisition. a minimum of 16 preamble bits is recommended. when the receiver is using the internal afc, the minimum recommended number of preamble bits is 48. the remaining fields that follow the preamble header do not have to use dc-free coding. for these fields, the adf7021 can accommodate coding schemes with a run length of up to eight bits without any performance degradation. if longer run lengths are required, an encoding scheme such as 8b/10b or manchester encoding is recommended. 4fsk preamble and data coding the recommended preamble bit pattern for 4fsk is a repeating 00100010 bit sequence. this 2-level sequence of repeating ?3, +3, ?3, +3 symbols is dc-free and maximizes the symbol timing performance and data recovery of the 4fsk preamble in the receiver. the minimum recommended length of the preamble is 32 bits (16 symbols). the remainder of the 4fsk packet should be constructed so that the transmitted symbols retain close to dc-free property by using data scrambling and/or by inserting specific dc balancing symbols in the transmitted bit stream at regular intervals, such as after every 8 or 16 symbols. 2fsk correlator demodulator and frequency errors the adf7021 has a number of options to combat frequency errors that exist due to mismatches between the transmit and receive crystals/tcxos. with afc disabled, the correlator demodulator is tolerant to frequency errors over the 0.4 f dev range, where f dev is the fsk frequency deviation. for larger frequency errors, the frequency tolerance can be widened to 0.8 f dev by adjusting the value of k and thus doubling the correlator bandwidth. k should then be calculated as ? ? ? ? ? ? ? ? = 2 10100 3 the discriminator_bw setting should also be recalculated using the new k value. doubling the correlator bandwidth to improve frequency error tolerance in this manner typically results in a 1 db to 2 db loss in receiver sensitivity. correlator demodulator and low modulation indices the modulation index in 2fsk is defined as ratedata f index modulation dev = 2 the receiver sensitivity performance can be maximized at low modulation index by increasing the discriminator bandwidth of the correlator demodulator. for modulation indices of less than 0.4, it is recommended to double the correlator bandwidth by calculating k as follows: ? ? ? ? ? ? ? ? = 2 e100 the discriminator_bw should be recalculated using the new k value. figure 26 highlights the improved sensitivity that can be achieved for 2fsk modulation, at low modulation indices, by doubling the correlator bandwidth. afc operation the adf7021 also supports a real-time afc loop that is used to remove frequency errors due to mismatches between the transmit and receive crystals/tcxos. the afc loop uses the linear frequency discriminator block to estimate frequency errors. the linear fsk discriminator output is filtered and averaged to remove the fsk frequency modulation using a combined averaging filter and envelope detector. in receive mode, the output of the envelope detector provides an estimate of the average if frequency. two methods of afc supported on the adf7021 are external and internal. external afc here, the user reads back the frequency information through the adf7021 serial port and applies a frequency correction value to the fractional-n synthesizer-n divider. the frequency information is obtained by reading the 16-bit signed afc readback, as described in the readback format section, and by applying the following formula: frequency readback [hz] = ( afc_readback demod clk )/2 18 although the afc_readback value is a signed number, under normal operating conditions, it is positive. in the absence of frequency errors, the frequency readback value is equal to the if frequency of 100 khz. internal afc the adf7021 supports a real-time, internal, automatic frequency control loop. in this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer-n divider using an internal proportional integral (pi) control loop. the internal afc control loop parameters are controlled in register 10 . the internal afc loop is activated by setting r10_db4 to 1. a scaling coefficient must also be entered, based on the crystal frequency in use. this is set up in r10_db[5:16] and should be calculated using ? ? ? ? ? ? ? ? = 5002 _ _ 24
adf7021 rev. a | page 37 of 64 maximum afc range the maximum frequency correction range of the afc loop is programmable on the adf7021. this is set by r10_db[24:31]. the maximum afc correction range is the difference in frequency between the upper and lower limits of the afc tuning range. for example, if the maximum afc correction range is set to 10 khz, the afc can adjust the receiver lo within the f lo 5 khz range. however, when rf_divide_by_2 (r1_db18) is enabled, the programmed range is halved. the user should account for this halving by doubling the programmed maximum afc range. the recommended maximum afc correction range should be 1.5 if filter bandwidth. if the maximum frequency correction range is set to be > 1.5 if bandwidth, the attenuation of the if filter can degrade the afc loop sensitivity. the adjacent channel rejection (acr) performance of the receivers can be degraded when afc is enabled and the afc correction range is close to the if filter bandwidth. however, because the afc correction range is programmable, the user can trade off correction range and acr performance. when afc errors are removed using either the internal or external afc, further improvement in receiver sensitivity can be obtained by reducing the if filter bandwidth using the if_bw bits (r4_db[30:31]). automatic sync word detection (swd) the adf7021 also supports automatic detection of the sync or id fields. to activate this mode, the sync (or id) word must be preprogrammed into the adf7021. in receive mode, this preprogrammed word is compared to the received bit stream. when a valid match is identified, the external swd pin is asserted by the adf7021 on the next rx clock pulse. this feature can be used to alert the microprocessor that a valid channel has been detected. it relaxes the computational requirements of the microprocessor and reduces the overall power consumption. the swd signal can also be used to frame the received packet by staying high for a preprogrammed number of bytes. the data packet length can be set in r12_db[8:15]. the swd pin status can be configured by setting r12_db[6:7]. r11_db[4:5] are used to set the length of the sync/id word, which can be 12, 16, 20, or 24 bits long. a value of 24 bits is recommended to minimize false sync word detection in the receiver that can occur during recovery of the remainder of the packet or when noise/no signal is present at the receiver input. the transmitter must transmit the sync byte msb first and the lsb last to ensure proper alignment in the receiver sync-byte-detection hardware. an error tolerance parameter can also be programmed that accepts a valid match when up to 3 bits of the word are incorrect. the error tolerance value is assigned in r11_db[6:7].
adf7021 rev. a | page 38 of 64 applications information if filter bandwidth calibration the if filter should be calibrated on every power-up in receive mode to correct for errors in the bandwidth and filter center frequency due to process variations. the automatic calibration requires no external intervention once it is initiated by a write to register 5. depending on numerous factors, such as if filter bandwidth, received signal bandwidth, and temperature variation, the user must determine whether to carry out a coarse calibration or a fine calibration. for information on calibration setup, refer to the if filter section. the performance of both calibration methods is outlined in table 21 . table 21. if filter calibration specifications filter calibration method center frequency accuracy 1 calibration time (typ) coarse cal 100 khz 2.5 khz 200 s fine cal 100 khz 0.5 khz 5.2 ms 1 after calibration. when to use coarse calibration it is recommended to perform a coarse calibration on every receive mode power-up. this calibration typically takes 200 s. the filter_cal_complete signal from muxout can be used to monitor the filter calibration duration or to signal the end of calibration. the adf7021 should not be accessed during calibration. when to use a fine calibration in cases where the receive signal bandwidth is very close to the bandwidth of the if filter, it is recommended to perform a fine filter calibration every time the unit powers up in receive mode. a fine calibration should be performed if obw + coarse calibration variation > if_filter_bw where: obw is the 99% occupied bandwidth of the transmit signal. coarse calibration variation is 2.5 khz. if_filter_bw is set by r4_db[30:31]. the filter_cal_complete signal from muxout (set by r0_db[29:31]) can be used to monitor the filter calibration duration or to signal the end of calibration. a coarse filter calibration is automatically performed prior to a fine filter calibration. when to use single fine calibration in applications where the receiver powers up numerous times in a short period, it is only necessary to perform a one-time fine calibration on the initial receiver power-up. after the initial coarse calibration and fine calibration, the result of the fine calibration can be read back through the serial interface using the filter_cal_readback result (refer to the filter bandwidth calibration readback section). on subsequent power-ups in receive mode, the filter is manually adjusted using the previous fine filter calibration result. this manual adjust is performed using the if_filter_adjust bits (r5_db[14:19]). this method should only be used if the successive power-ups in receive mode are over a short duration, during which time there is little variation in temperature (>15c). if filter variation with temperature when calibrated, the filter center frequency can vary with changes in temperature. if the adf7021 is used in an application where it remains in receive mode for a considerable length of time, the user must consider this variation of filter center frequency with temperature. this variation is typically 0.7 khz per 10c, which means that if a coarse filter calibration and fine filter calibration are performed at 25c, the initial maximum error is 0.5 khz, and the maximum possible change in the filter center frequency over temperature (?40c and +85c) is 4.5 khz. this gives a total error of 5 khz. if the receive signal occupied bandwidth is considerably less than the if filter bandwidth, the variation of filter center frequency over the operating temperature range may not be an issue. alternatively, if the if filter bandwidth is not wide enough to tolerate the variation with temperature, a periodic filter calibration can be performed, or alternatively, the on-chip temperature sensor can be used to determine when a filter cali- bration is necessary by monitoring for changes in temperature. lna/pa matching the adf7021 exhibits optimum performance in terms of sensitivity, transmit power, and current consumption, only if its rf input and output ports are properly matched to the antenna impedance. for cost sensitive applications, the adf7021 is equipped with an internal rx/tx switch that facilitates the use of a simple, combined passive pa/lna matching network. alternatively, an external rx/tx switch such as the adg919 can be used, which yields a slightly improved receiver sensitivity and lower transmitter power consumption. internal rx/tx switch figure 49 shows the adf7021 in a configuration where the internal rx/tx switch is used with a combined lna/pa matching network. this is the configuration used on the eval- adf7021dbx evaluation board. for most applications, the slight performance degradation of 1 db to 2 db caused by the internal rx/tx switch is acceptable, allowing the user to take advantage of the cost saving potential of this solution. the design of the combined matching network must compensate for the reactance presented by the networks in the tx and the rx paths, taking the state of the rx/tx switch into consideration.
adf7021 rev. a | page 39 of 64 pa lna pa_out rfin rfinb v bat l1 adf7021 optional bpf or lpf l a c a c1 c b z in _rfin z opt _pa z in _rfin a ntenna 05876-022 05876-021 figure 49. adf7021 with internal rx/tx switch the procedure typically requires several iterations until an acceptable compromise has been reached. the successful imple- mentation of a combined lna/pa matching network for the adf7021 is critically dependent on the availability of an accurate electrical model for the pcb. in this context, the use of a suitable cad package is strongly recommended. to avoid this effort, a small form-factor reference design for the adf7021 is provided, including matching and harmonic filter components. the design is on a 2-layer pcb to minimize cost. gerber files are available at www.analog.com . external rx/tx switch figure 50 shows a configuration using an external rx/tx switch. this configuration allows an independent optimization of the matching and filter network in the transmit and receive path. therefore, it is more flexible and less difficult to design than the configuration using the internal rx/tx switch. the pa is biased through inductor l1, while c1 blocks dc current. together, l1 and c1 form the matching network that transforms the source impedance into the optimum pa load impedance, z opt _pa. pa lna pa_out rfin rfinb v bat l1 adf7021 adg919 optional bpf (saw) optional lpf l a c a c1 c b z in _rfin z opt _pa z in _rfin antenna rx/tx ? select figure 50. adf7021 with external rx/tx switch z opt _pa depends on various factors, such as the required output power, the frequency range, the supply voltage range, and the temperature range. selecting an appropriate z opt _pa helps to minimize the tx current consumption in the application. application note an-764 contains a number of z opt _pa values for representative conditions. under certain conditions, however, it is recommended to obtain a suitable z opt _pa value by means of a load-pull measurement. due to the differential lna input, the lna matching network must be designed to provide both a single-ended-to-differential conversion and a complex, conjugate impedance match. the network with the lowest component count that can satisfy these requirements is the configuration shown in figure 50 , consisting of two capacitors and one inductor. a first-order implementation of the matching network can be obtained by understanding the arrangement as two l-type matching networks in a back-to- back configuration. due to the asymmetry of the network with respect to ground, a compromise between the input reflection coefficient and the maximum differential signal swing at the lna input must be established. the use of appropriate cad software is strongly recommended for this optimization. depending on the antenna configuration, the user may need a harmonic filter at the pa output to satisfy the spurious emission requirement of the applicable government regulations. the harmonic filter can be implemented in various ways, such as a discrete lc pi or t-stage filter. dielectric low-pass filter components, such as the lfl18924mtc1a052 (for operation in the 915 mhz and 868 mhz band) by murata manufacturing co. ltd., represent an attractive alternative to discrete designs. the immunity of the adf7021 to strong out-of-band interference can be improved by adding a band-pass filter in the rx path. apart from discrete designs, saw or dielectric filter components such as the safch869mam0t00, safch915mal0n00, dcfb2869mlejaa-tt1, or dcfb3915mldjaa-tt1, all by murata manufacturing co. ltd., are well-suited for this purpose. alternatively, the adf7021 blocking performance can be improved by selecting one of the enhanced linearity modes, as described in table 14 . image rejection calibration the image channel in the adf7021 is 200 khz below the desired signal. the polyphase filter rejects this image with an asymme- tric frequency response. the image rejection performance of the receiver is dependent on how well matched the i and q signals are in amplitude, and how well matched the quadrature is between them (that is, how close to 90 apart they are). the uncalibrated image rejection performance is approximately 29 db (at 450 mhz). however, it is possible to improve on this performance by as much as 20 db by finding the optimum i/q gain and phase adjust settings. calibration using internal rf source with the lna powered off, an on-chip generated, low level rf tone is applied to the mixer inputs. the lo is adjusted to make the tone fall at the image frequency where it is attenuated by the image rejection of the if filter. the power level of this tone is then measured using the rssi readback. the i/q gain and phase adjust dacs (r5_db[20:31]) are adjusted and the rssi is remeasured. this process is repeated until the optimum values for the gain and phase adjust are found that provide the lowest rssi readback level, thereby maximizing the image rejection performance of the receiver.
adf7021 rev. a | page 40 of 64 internal signal source mux rfin rfinb lna adf7021 polyphase if filter phase adjust gain adjust i q from lo gain adjust register 5 phase adjust register 5 serial interface 4 microcontroller 4 rssi/ log amp 7-bit adc rssi readback i/q gain/phase adjust and rssi measurement algorithm 05876-072 figure 51. image rejection calibration using the internal calibration source and a microcontroller using the internal rf source, the rf frequencies that can be utilized for image calibration are programmable and are odd multiples of the reference frequency. calibration using external rf source ir calibration can also be implemented using an external rf source. the ir calibration procedure is the same as that used for the internal rf source, except that an rf tone is applied to the lna input. calibration proc edure and setup the ir calibration algorithm available from analog devices, inc. is based on a low complexity, 2d optimization algorithm that can be implemented in an external microprocessor or microcontroller. to enable the internal rf source, the ir_cal_source_ drive_level bits (r6_db[28:29]) should be set to the maximum level. the lna should be set to its minimum gain setting, and the agc should be disabled if the internal source is being used. alternatively, an external rf source can be used. the magnitude of the phase adjust is set by using the ir_phase_ adjust_mag bits (r5_db[20:23]). this correction can be applied to either the i channel or q channel, depending on the value of the ir_phase_adjust_direction bit (r5_db24). the magnitude of the i/q gain is adjusted by the ir_gain_ adjust_mag bits (r5_db[25:29]). this correction can be applied to either the i or q channel, depending on the value of ir_gain_adjust_i/q bit (r5_db30), whereas the ir_gain_adjust_up/dn bit (r5_db31) sets whether the gain adjustment defines a gain or an attenuation adjust. the calibration results are valid over changes in the adf7021 supply voltage. however, there is some variation with temperature. a typical plot of variation in image rejection over temperature after initial calibrations at ?40c, +25c, and +85c is shown in figure 52 . the internal temperature sensor on the adf7021 can be used to determine if a new ir calibration is required. 0 10 20 30 40 50 60 ?60 ?40 ?20 0 20 40 60 80 100 v dd = 3.0v if bw = 25khz wanted signal: rf freq = 430mhz modulation = 2fsk data rate = 9.6kbps, prbs9 f dev = 4khz level= ?100dbm interferer signal: rf freq = 429.8mhz modulation = 2fsk data rate = 9.6kbps, prbs11 f dev = 4khz 05876-067 temperature (c) image rejection (db) cal at +25c cal at +85c cal at ?40c figure 52. image rejection variation with temperature after initial calibrations at ?40c, +25c, and +85c
adf7021 rev. a | page 41 of 64 packet structure and coding the suggested packet structure to use with the adf7021 is shown in figure 53 . preamble sync word id field data field crc 05876-023 figure 53. typical format of a transmit protocol refer to the receiver setup section for information on the required preamble structure and length for the various modulation schemes. programming after initial power-up table 22 lists the minimum number of writes needed to set up the adf7021 in either tx or rx mode after ce is brought high. additional registers can also be written to tailor the part to a particular application, such as setting up sync byte detection or enabling afc. when going from tx to rx or vice versa, the user needs to toggle the tx/rx bit and write only to register 0 to alter the lo by 100 khz. table 22. minimum register writ es required for tx/rx setup mode registers tx reg 1 reg 3 reg 0 reg 2 rx reg 1 reg 3 reg 0 reg 5 reg 4 tx to rx and rx to tx reg 0 the recommended programming sequences for transmit and receive are shown in figure 54 and figure 55 , respectively. the difference in the power-up routine for a tcxo and xtal reference is shown in these figures.
adf7021 rev. a | page 42 of 64 power-down ce low xtal reference tcxo reference ce high wait 10s (regulator power-up) write to register 1 (turns on vco) wait 0.7ms (typical vco settling) write to register 0 (turns on pll) wait 40s (typical pll settling) write to register 2 (turns on pa) wait for pa to ramp up (only if pa ramp enabled) wait for tx latency number of bits (refer to table 12) write to register 2 (turns off pa) wait for pa to ramp down write to register 3 (turns on tx/rx clocks) ce high wait 10s + 1ms (regulator power-up + typical xtal settling) ce low power-down tx mode optional. only necessary if pa ramp down is required. 05876-086 figure 54. power-up sequence for transmit mode
adf7021 rev. a | page 43 of 64 power-down ce low write to register 5 (starts if filter calibration) wait 0.2ms (coarse cal) or wait 5.2ms (coarse calibration + fine calibration) write to register 11 (set up swd) write to register 12 (enable swd) write to register 6 (sets up if filter calibration) ce low power-down rx mode write to register 3 (turns on tx/rx clocks) write to register 4 (turns on demod) write to register 10 (turns on afc) optional. 05876-087 write to register 0 (turns on pll) wait 40s (typical pll settling) ce high wait 10s (regulator power-up) write to register 1 (turns on vco) wait 0.7ms (typical vco settling) ce high wait 10s + 1ms (regulator power-up + typical xtal settling) xtal reference tcxo reference optional: only necessary if afc is required. optional: only necessary if swd is required. optional: only necessary if if filter fine cal is required. figure 55. power-up sequence for receive mode
adf7021 rev. a | page 44 of 64 applicatons circuit the adf7021 requires very few external components for operation. figure 56 shows the recommended application circuit. note that the power supply decoupling and regulator capacitors are omitted for clarity. for recommended component values, refer to the adf7021 evaluation board data sheet and an-915 application note accessible from the adf7021 product page. follow the reference design schematic closely to ensure optimum performance in narrow-band applications. 48 47 46 45 44 43 42 41 40 39 38 37 adf7021 vcoin creg1 vdd1 rfout rfgnd rfin rfinb r lna vdd4 rset creg4 gnd4 cvco gnd1 l1 gnd l2 vdd cpout creg3 vdd3 osc1 osc2 muxout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 mix_i mix_i mix_q mix_q filt_i filt_i gnd4 filt_q filt_q gnd4 test_a ce clkout txrxdata txrxclk swd vdd2 creg2 adcin gnd2 sclk sread sdata sle 36 35 34 33 32 31 30 29 28 27 26 25 vdd vdd vdd tcxo vdd vdd vdd antenna connection to microcontroller tx/rx signal interface to microcontroller configuration interface t-stage lc filter matching loop filter cvco cap ext vco l* reference rset resistor rlna resistor chip enable to microcontroller *pin 44 and pin 46 can be left floating if external inductor vco is not used. notes 1. pins [13:18], pins [20:21], and pin 23 are test pins and are not used in normal operation. 05876-084 figure 56. typical application circuit (regulator capacitors and power supply decoupling not shown)
adf7021 rev. a | page 45 of 64 serial interface the serial interface allows the user to program the 16-/32-bit registers using a 3-wire interface (sclk, sdata, and sle). it consists of a level shifter, 32-bit shift register, and 16 latches. signals should be cmos compatible. the serial interface is powered by the regulator, and, therefore, is inactive when ce is low. data is clocked into the register, msb first, on the rising edge of each clock (sclk). data is transferred to one of 16 latches on the rising edge of sle. the destination latch is determined by the value of the four control bits (c4 to c1); these are the bottom 4 lsbs, db3 to db0, as shown in figure 2 . data can also be read back on the sread pin. readback format the readback operation is initiated by writing a valid control word to the readback register and enabling the readback bit (r7_db8 = 1). the readback can begin after the control word has been latched with the sle signal. sle must be kept high while the data is being read out. each active edge at the sclk pin successively clocks the readback word out at the sread pin, as shown in figure 57 , starting with the msb first. the data appearing at the first clock cycle following the latch operation must be ignored. an extra clock cycle is needed after the 16 th readback bit to return the sread pin to tristate. therefore, 18 total clock cycles are needed for each read back. after the 18 th clock cycle, sle should be brought low. afc readback the afc readback is valid only during the reception of fsk signals with either the linear or correlator demodulator active. the afc readback value is formatted as a signed 16-bit integer comprising bit rv1 to bit rv16 and is scaled according to the following formula: freq rb [hz] = ( afc_readback demod clk )/2 18 in the absence of frequency errors, freq rb is equal to the if frequency of 100 khz. note that, for the afc readback to yield a valid result, the down converted input signal must not fall outside the bandwidth of the analog if filter. at low input signal levels, the variation in the readback value can be improved by averaging. rssi readback the format of the readback word is shown in figure 57 . it comprises the rssi-level information (bit rv1 to bit rv7), the current filter gain (fg1, fg2), and the current lna gain (lg1, lg2) setting. the filter and lna gain are coded in accordance with the definitions in the register 9agc register section. for signal levels below ?100 dbm, averaging the measured rssi values improves accuracy. the input power can be calculated from the rssi readback value as outlined in the rssi/agc section. battery voltage/adcin/temperature sensor readback the battery voltage is measured at pin vdd4. the readback information is contained in bit rv1 to bit rv7. this also applies for the readback of the voltage at the adcin pin and the temperature sensor. from the readback information, the battery or adcin voltage can be determined using v battery = ( battery_voltage_readback )/21.1 v adcin = ( adcin_voltage_readback )/42.1 the temperature can be calculated using temp [c] = ?40 + (68.4 ? temp_readback ) 9.32 silicon revision readback the silicon revision readback word is valid without setting any other registers. the silicon revision word is coded with four quartets in bcd format. the product code (pc) is coded with three quartets extending from bit rv5 to bit rv16. the revision code (rc) is coded with one quartet extending from bit rv1 to bit rv4. the product code for the adf7021 should read back as pc = 0x210. the current revision code should read as rc = 0x4. filter bandwidth calibration readback the filter calibration readback word is contained in bit rv1 to bit rv8. this readback can be used for manual filter adjust, thereby avoiding the need to do an if filter calibration in some instances. the manual adjust value is programmed by r5_db[14:19]. to calculate the manual adjust based on a filter calibration readback, use the following formula: if_filter_adjust = filter_cal_readback ? 128 the result should be programmed into r5_db[14:19] as outlined in the register 5if filter setup register section. readback mode afc readback db15 rv16 x x rv16 0 rssi readback battery voltage/adcin/ temp. sensor readback silicon revision filter cal readback readback value db14 rv15 x x rv15 0 db13 rv14 x x rv14 0 db12 rv13 x x rv13 0 db11 rv12 x x rv12 0 db10 rv11 lg2 x rv11 0 db9 rv10 lg1 x rv10 0 db8 rv9 fg2 x rv9 0 db7 rv8 fg1 x rv8 rv8 db6 rv7 rv7 rv7 rv7 rv7 db5 rv6 rv6 rv6 rv6 rv6 db4 rv5 rv5 rv5 rv5 rv5 db3 rv4 rv4 rv4 rv4 rv4 db2 rv3 rv3 rv3 rv3 rv3 db1 rv2 rv2 rv2 rv2 rv2 db0 rv1 rv1 rv1 rv1 rv1 05876-029 figure 57. readback value table
adf7021 rev. a | page 46 of 64 05876-026 interfacing to microcontroller/dsp standard transmit/receive data interface the standard transmit/receive signal and configuration interface to a microcontroller is shown in figure 58 . in transmit mode, the adf7021 provides the data clock on the txrxclk pin, and the txrxdata pin is used as the data input. the transmit data is clocked into the adf7021 on the rising edge of txrxclk. miso aduc84x adf7021 mosi sclock ss p3.7 p3.2/int0 p2.4 txrxdata txrxclk ce swd sread p2.5 sle p2.6 p2.7 sdata sclk gpio figure 58. aduc84x to adf7021 connection diagram in receive mode, the adf7021 provides the synchronized data clock on the txrxclk pin. the receive data is available on the txrxdata pin. the rising edge of txrxclk should be used to clock the receive data into the microcontroller. refer to figure 4 and figure 5 for the relevant timing diagrams. in 4fsk transmit mode, the msb of the transmit symbol is clocked into the adf7021 on the first rising edge of the data clock from the txrxclk pin. in 4fsk receive mode, the msb of the first payload symbol is clocked out on the first negative edge of the data clock after the swd, and should be clocked into the microcontroller on the following rising edge. refer to figure 6 and figure 7 for the relevant timing diagrams. uart mode in uart mode, the txrxclk pin is configured to input transmit data in transmit mode. in receive mode, the receive data is available on the txrxdata pin, thus providing an asynchronous data interface. the uart mode can only be used with oversampled 2fsk. figure 59 shows a possible interface to a microcontroller using the uart mode of the adf7021. to enable this uart interface mode, set r0_db28 high. figure 8 and figure 9 show the relevant timing diagrams for uart mode. uart adf7021 txrxclk txrxdata txdata rxdata ce swd sread sle sdata sclk gpio microcontroller 05876-085 figure 59. adf7021(uart mode) to asynchronous microcontroller interface spi mode in spi mode, the txrxclk pin is configured to input transmit data in transmit mode. in receive mode, the receive data is available on the txrxdata pin. the data clock in both transmit and receive modes is available on the clkout pin. in transmit mode, data is clocked into the adf7021 on the positive edge of clkout. in receive mode, the txrxdata data pin should be sampled by the microcontroller on the positive edge of the clkout. to enable spi interface mode, set r0_db28 high and set r15_db[17:19] to 0x7. figure 8 and figure 9 show the relevant timing diagrams for spi mode, while figure 60 shows the recommended interface to a microcontroller using the spi mode of the adf7021. spi adf7021 txrxclk txrxdata miso mosi microcontroller ce swd sread sle sdata sclk gpio sclk clkout 05876-076 05876-027 figure 60. adf7021 (spi mode) to microcontroller interface adsp-bf533 interface the suggested method of interfacing to the blackfin? adsp- bf533 is given in figure 61 . a mosi adsp-bf533 df7021 miso pf5 rsclk1 dt1pri dr1pri rfs1 pf6 sdata sle txrxdata swd ce sck sclk sread txrxclk figure 61. adsp-bf533 to adf7021 connection diagram
adf7021 rev. a | page 47 of 64 register 0n register tr1 transmit/ receive 0 transmit receive 1 m3 m2 m1 muxout 0 regulator_ready (default) filter_cal_complete 0 0 digital_lock_detect 0 rssi_ready 1t x _ r x 1l o g i c _ z e r o 1t r i s t a t e 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1logic_one u1 uart mode 0disabled 1 enabled n8 n7 n6 n5 n4 n3 n2 n1 n counter divide ratio 02 3 02 4 . . . 1 253 1 254 0 0 . . . 1 1 0 0 . . . . . . 1 1 1 1 1 1 . . . 0 1 1 1 . . . 1 0 1 1 . . . 1 0 0 1 . . . . . . 1 0 1 0 1 1 1 1 1 1 1 1 255 15-bit fractional_n 8-bit integer_n tx/rx uart mode muxout address bits n5 n4 n8 m5 m6 m7 m8 m12 m13 m15 n1 n2 n3 m14 m9 m10 m11 m4 m3 tr1 u1 m1 m3 m2 c2 (0) c1 (0) c3 (0) c4 (0) m1 m2 n7 n6 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 fractional divide ratio 0 1 2 . . . 32764 32765 32766 32767 m15 0 0 0 . . . 1 1 1 1 m14 0 0 0 . . . 1 1 1 1 m13 0 0 0 . . . 1 1 1 1 ... ... ... ... ... ... ... ... ... ... ... m3 0 0 0 . . . 1 1 1 1 m2 0 0 1 . . . 0 0 1 1 m1 0 1 0 . . . 0 1 0 1 05876-0 30 figure 62. register 0n register map the rf output frequency is calculated by the following: for the direct output ? ? ? ? ? ? + = 15 2 _ _ n fractional ninteger pfd rf out for the rf_divide_by_2 (db18) selected ? ? ? ? ? ? + = 15 2 _ _ 5.0 n fractional ninteger pfd rf out in uart/spi mode, the txrxclk pin is used to input the tx data. the rx data is available on the txrxdata pin. in the muxout map in figure 62 , the filter_cal_complete indicates when a coarse or coarse plus fine if filter calibration has finished. the digital_lock_detect indicates when the pll has locked. the rssi_ready indicates that the rssi signal has settled and an rssi readback can be performed. tx_rx gives the status of db27 in this register, which can be used to control an external tx/rx switch.
adf7021 rev. a | page 48 of 64 0587 register 1vco/oscillator register 6-031 r3 r2 r1 rf r counter divide ratio 0 0 . . . 1 1 2 . . . 7 1 0 . . . 1 0 1 . . . 1 x1 xtal osc 0off 1on va2 va1 vco center freq adjust 0 nominal 0 vco adjust up 1 1 vco adjust up 2 1 0 1 0 1 vco adjust up 3 d1 xtal doubler 0 disable enabled 1 cp2 cp1 rset i cp (ma) 3.6k ? 000.3 010.9 101.5 112.1 vb4 vb3 vb2 vb1 vco bias current 0 0.25ma 00 . 5 m a . 1 1 0 . 1 0 1 . 1 0 0 . 1 3.75ma cl4 cl3 cl2 cl1 clkout divide ratio 0 off 0 0 . . . 1 0 1 0 . . . 1 2 4 . . . 0 0 1 . . . 1 0 0 0 . . . 1 30 vco_bias cp_ current rf_divide_ by_2 xosc_ enable vco_ enable address bits xtal_ doubler xtal_ bias vco_ adjust va1 vb4 cl1 cl2 cl3 cl4 cp1 cp2 rfd1 vb1 vb2 vb3 ve1 x1 xb1 xb2 d1 r3 c2 (0) c1 (1) c3 (0) c4 (0) r1 r2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 va2 db24 db1 db0 db2 db3 xb2 xb1 xtal bias 02 0 a 02 5 a 13 0 a 0 1 0 1 135a rfd1 rf divide by 2 0off on 1 loop condition vco off vco on ve1 0 1 db25 vcl1 vco_ inductor vco internal l vco external l vco vcl1 0 1 r_counter clockout_ divide figure 63. register 1vco/ oscillator register map the r_counter and xtal_doubler relationship is expressed as follows: if xtal_doubler = 0, counter r xtal pfd _ if xt al_doubler =1, counter r xtal pfd _ 2 u the clockout_divide is a divided-down and inverted version of the xtal and is available on pin 36 (clkout). set xosc_enable high when using an external crystal. if using an external oscillator (such as tcxo) with cmos-level outputs into pin osc2, set xosc_enable low. if using an external oscillator with a 0.8 v p-p clipped sine wave output into pin osc1, set xosc_enable high. the vco_bias bits should be set according to table 9 . the vco_adjust bits adjust the center of the vco operating band. each bit typically adjusts the vco band up by 1% of the rf operating frequency (0.5% if rf_divide_by_2 is enabled). setting vco_inductor to external allows the use of the external inductor vco, which gives rf operating frequencies of 80 hz to 650 mhz. if the internal inductor vco is being used for operation, set this bit low.
adf7021 rev. a | page 49 of 64 05876-032 register 2transmit modulation register p6 0 0 0 0 . . 1 . . . . . . . . . . . . . . . 1 p2 0 0 1 1 . . 1 p1 0 1 0 1 . . 1 0 (pa off) 1 (?16.0 dbm) 2 3 . . 63 (13 dbm) tfd9 0 0 0 0 . 1 tfd3 0 0 0 0 . 1 ... ... ... ... ... ... ... tfd2 0 0 1 1 . 1 tfd1 0 1 0 1 . 1 0 1 2 3 . 511 tx_frequency_deviation power_amplifier txdata_ invert pa_bias pa_ramp modulation_ scheme address bits pa_ enable pe1 0 1 power amplifier off on pa2 0 0 1 1 pa1 0 1 0 1 pa bias 5a 7a 9a 11 a di2 0 0 1 1 di1 0 1 0 1 txdata invert normal invert clk invert data inv clk and data s3 0 0 0 0 1 1 1 1 s2 0 0 1 1 0 0 1 1 modulation scheme 2fsk gaussian 2fsk 3fsk 4fsk oversampled 2fsk raised cosine 2fsk raised cosine 3fsk raised cosine 4fsk s1 0 1 0 1 0 1 0 1 pr3 0 0 0 0 1 1 1 1 pr2 0 0 1 1 0 0 1 1 pa ramp rate no ramp 256 codes/bit 128 codes/bit 64 codes/bit 32 codes/bit 16 codes/bit 8 codes/bit 4 codes/bit pr1 0 1 0 1 0 1 0 1 tfd5 tfd4 tfd8 pr1 pr2 pr3 pa1 p3 p4 p6 tfd1 tfd2 tfd3 p5 pa2 p1 p2 pe1 s3 tfd9 di1 di2 c2 (1) c1 (0) c3 (0) c4 (0) s1 s2 tfd7 tfd6 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 r-cosine_ alpha db30 nrc1 nrc1 0 1 raised cosine alpha 0.7 0.5 (default) f dev pa level figure 64. register 2transmit modulation register map the 2fsk/3fsk/4fsk frequency deviation is expressed by the following: direct output frequency deviation [hz] = 16 2 pfdon cy_deviati tx_frequen with rf_divide_by_2 (r1_db18) enabled frequency deviation [hz] = 16 2 5.0 pfdon cy_deviati tx_frequen where tx_frequency_deviation is set by db[19:27] and pfd is the pfd frequency. in the case of 4fsk, there are tones at 3 the frequency deviation and at 1 the deviation. the power amplifier (pa) ramps at the programmed rate (r2_db[8:10]) until it reaches its programmed level db[13:18]. if the pa is enabled/disabled by the pa_enable bit (db7), it ramps up and down. if it is enabled/disabled by the tx/rx bit (r0_db27), it ramps up and turns hard off. r-cosine_alpha sets the roll-off factor (alpha) of the raised cosine data filter to either 0.5 or 0.7. the alpha is set to 0.5 by default, but the raised cosine filter bandwidth can be increased to provide less aggressive data filtering by using an alpha of 0.7.
adf7021 rev. a | page 50 of 64 05876-0 1 1 1 1 1 1 ... ... 1 1 0 1 254 255 register 3transmit/receive clock register 33 fs8 0 0 . fs7 0 0 . fs3 0 0 . ... ... ... ... fs2 0 1 . fs1 1 0 . cdr clk divide 1 2 . bk2 0 0 1 1 bk1 0 1 0 1 bbos clk divide 4 8 16 32 sk8 0 0 . 1 1 sk7 0 0 . 1 1 sk3 0 0 . 1 1 ... ... ... ... ... ... sk2 0 1 . 1 1 sk1 1 0 . 0 1 seq clk divide 1 2 . 254 255 ok2 0 0 ... 1 ok1 0 1 ... 1 demod clk divide invalid 1 ... 15 sequencer_clk_divide agc_clk_divide cdr_clk_divide bbos_clk_ divide dem_clk_ divide address bits gd6 0 0 ... 1 gd5 0 0 ... 1 gd3 0 0 ... 1 gd4 0 0 ... 1 gd2 0 0 ... 1 gd1 0 1 ... 1 agc clk divide invalid 1 ... 127 sk8 sk7 fs1 fs2 fs3 fs4 fs8 sk1 sk3 sk4 sk5 sk6 sk2 fs5 fs6 fs7 ok2 ok1 ok4 ok3 c2 (1) c1 (1) c3 (0) c4 (0) bk1 bk2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 gd6 gd5 gd1 gd2 gd3 gd4 db24 db25 db28 db27 db26 db29 db30 db31 db1 db0 db2 db3 ok3 0 0 ... 1 0 0 ... 1 ok4 figure 65. register 3transmit/receive clock register map baseband offset clock frequency (bbos clk) must be greater than 1 mhz and less than 2 mhz, where divide clkbbos xtal clkbbos __ = set the demodulator clock (demod clk) such that 2 mhz demod clk 15 mhz, where divide clk demod xtal clk demod __ = for 2fsk/3fsk, the data/clock recovery frequency (cdr clk) needs to be within 2% of (32 data rate). for 4fsk, the cdr clk needs to be within 2% of (32 symbol rate). divide clkcdr clk demod clkcdr __ = the sequencer clock (seq clk) supplies the clock to the digital receive block. it should be as close to 100 khz as possible. divide clkseq xtal clkseq __ = the time allowed for each agc step to settle is determined by the agc update rate. it should be set close to 10 khz. divide clkagc clkseq rate update agc __ [hz] =
adf7021 rev. a | page 51 of 64 05876- register 4demodulator setup register 034 discriminator_bw dot_product post_demod_bw rx_ invert if_bw address bits td4 td3 ri1 ri2 dw1 dw2 dw6 dw7 dw9 dw10 td1 td2 dw8 dw3 dw4 dw5 dp1 ds3 c2(0) c1(0) c3(1) c4(0) ds1 ds2 td6 td5 td10 td9 td7 td8 ifb2 ifb1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 ds1 0 1 0 1 0 1 0 1 demodulator scheme 2fsk linear demodulator 2fsk correlator demodulator 3fsk demod 4fsk demod reserved reserved reserved reserved dp1 0 1 product cross product dot product ri1 0 1 0 1 invert normal invert clk invert data invert clk/data ifb1 0 1 0 1 if filter bw 12.5khz 18.75khz 25khz invalid ds2ds3 0 0 1 1 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 ri2 ifb2 0 0 1 1 dw3 0 0 . . . . 1 dw1 1 0 . . . . 1 post demod bw 1 2 . . . . 1023 dw2 0 1 . . . . 1 dw10 0 0 . . . . 1 dw6 0 0 . . . . 1 . . . . . . . . dw5 0 0 . . . . 1 dw4 0 0 . . . . 1 td3 0 0 . . . td1 1 0 . . . correlator discrim bw 1 2 . . . td2 0 1 . . . td10 0 0 . . . td6 0 0 . . . . . . . . . td5 0 0 . . . td4 0 0 . . . . 1 . 0 . 660 . 0 . 1 . 0 . . . 1 . 0 demod_ scheme figure 66. register 4demodulator setup register map to solve for discriminator_bw, use the following equation: discriminator_bw = 3 10400 where the maximum value = 660. for 2fsk, ? ? ? ? ? ? ? ? = 3 10100 for 3fsk, ? ? ? ? ? ? ? ? = 2 10100 3 for 4fsk, ? ? ? ? ? ? ? ? = 4 10100 3 4 where: round is rounded to the nearest integer. round 4fsk is rounded to the nearest of the following integers: 32, 31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3. f dev is the transmit frequency deviation in hz. for 4fsk, f dev is the frequency deviation used for the 1 symbols (that is, the inner frequency deviations). rx_invert (db[8:9]) and dot_product (db7) need to be set as outlined in table 17 and table 18 . clk demod f _bw post_demod cutoff = 2 11 where the cutoff frequency ( f cutoff ) of the post demodulator filter should typically be 0.75 the data rate in 2fsk. in 3fsk, it should be set equal to the data rate, while in 4fsk, it should be set equal to 1.6 symbol rate.
adf7021 rev. a | page 52 of 64 0587 register 5if filter setup register 6-035 ir_phase_ adjust_mag ir phase adjust direction ir gain adjust i/q ir gain adjust up/dn ir_gain_ adjust_mag if_filter_divider if_cal_coarse if_filter_adjust address bits ifa1 ifd9 ifd5 ifd6 pm2 pm3 gm1 gm2 gm4 gm5 ifd7 ifd8 gm3 pm4 pd1 ifd4 ifd3 c2 (0) c1 (1) c3 (1) c4 (0) ifd1 cc1 ifd2 ifa3 ifa2 pm1 ifa6 ifa4 ifa5 ga1 gq1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 cc1 0 1 cal no cal do cal pd1 0 1 ir phase adjust i/q adjust i ch adjust q ch ga1 0 ir gain adjust up/dn gain 1 attenuate gq1 0 1 ir gain adjust i/q adjust i ch adjust q ch ifd3 0 0 . . . . 1 ifd1 1 0 . . . . 1 filter clock divide ratio 1 2 . . . . 511 ifd2 0 1 . . . . 1 ifa2 0 0 1 .. 1 0 0 1 . 1 if filter adjust ifa6 0 0 0 .. 0 1 1 1 1 1 gm3 ir gain adjust gm5 0 0 0 . 1 ifd9 0 0 . . . . 1 ifd6 0 0 . . . . 1 . . . . . . . . ifd5 0 0 . . . . 1 ifd4 0 0 . . . . 1 0 1 0 .. 1 0 1 0 . 1 ifa1 ... ... ... ... ... ... ... ... ... ... ... 0 +1 +2 ... +31 0 ?1 ?2 ... ?31 gm4 gm2 gm1 0 0 0 . 1 0 0 0 . 1 0 0 1 . 1 0 1 0 . 1 0 1 2 ... 31 pm2 ir phase adjust pm3 pm1 pm1 0 0 0 . 1 0 0 0 . 1 0 0 1 . 1 0 1 0 . 1 0 1 2 ... 15 ifa5 0 0 0 .. 1 0 0 0 . 1 figure 67. register 5if filter setup register map a coarse if filter calibration is performed when the if_cal_coarse bit (db4) is set. if the if_fine_cal bit (r6_db4) has been previously set, a fine if filter calibration is automatically performed after the coarse calibration. set if_filter_divider such that khz50 __ = if_filter_adjust allows the if fine filter calibration result to be programmed directly on subsequent receiver power-ups, thereby saving on the need to redo a fine filter calibration in some instances. refer to the filter bandwidth calibration readback section for information about using the if_filter_adjust bits. db[20:31] are used for image rejection calibration. refer to the image rejection calibration section for details on how to program these parameters.
adf7021 rev. a | page 53 of 64 0587 register 6if fine cal setup register 6-036 if_cal_lower_tone_divide if_cal_upper_tone_divide if_cal_dwell_time if_fine_ cal address bits cd3 cd2 cd6 lt4 lt5 lt6 lt7 ut3 ut4 ut6 ut7 ut8 cd1 ut5 lt8 ut1 ut2 lt3 lt2 cd7 c2 (1) c1 (0) c3 (1) c4 (0) fc1 lt1 cd5 cd4 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db25 db1 db0 db2 db3 fc1 0 1 if fine cal disabled enabled ut3 0 0 0 . . 1 ut1 1 0 1 . . 1 if cal upper tone divide 1 2 3 . . ut2 0 1 1 . . 1 ut8 0 0 0 . . 0 ... ... ... ... ... ... ... 127 lt3 0 0 0 . . 1 lt1 1 0 1 . . 1 1 2 3 . . lt2 0 1 1 . . 1 lt8 0 0 0 . . 1 ... ... ... ... ... ... ... 255 if cal lower tone divide cd3 0 0 0 . . cd1 1 0 1 . . if cal dwell time 1 2 3 . . cd2 0 1 1 . . cd7 0 0 0 . . ... ... ... ... ... ... 1 11 1 ... 127 db28 irc1 db29 db30 irc2 ird1 ir_cal_ source_ drive_level ir_cal_ source 2 irc1 0 1 0 1 ir cal source drive level irc2 0 0 1 1 off low med high ird1 0 1 ir cal source 2 source 2 off source 2 on 0 0 0 . . 1 lt7 0 0 0 . . 1 ut7 figure 68. register 6if fine cal setup register map a fine if filter calibration is set by enabling the if_fine_cal bit (r6_db4). a fine calibration is then carried out only when register 5 is written to and r5_db4 is set. set the if upper and lower tones used during fine filter calibration as follows: khz8.65 2 ____ = khz5.131 2 ____ = the if tone calibration time is the amount of time that is spent at an if calibration tone. it is dependent on the sequencer clock. for best practice, is recommended to have the if tone calibration time be at least 500 s. clkseq time dwell calif timencalibratio toneif ___ = the total time for a fine if filter calibration is if tone calibration time 10. db[28:30] control the internal source for the image rejection (ir) calibration. the ir_c al_source_drive_level bits (db[28:29]) set the drive strength of the source, whereas the ir_cal_source_2 bit (db30) allows the frequency of the internal signal source to be divided by 2.
adf7021 rev. a | page 54 of 64 register 7readback setup register ad1 ad2 rb1 rb2 rb3 db8 db7 db6 db5 db4 db3 db2 c2 (1) c1 (1) control bits db1 db0 c3 (1) c4 (0) readback select adc mode ad2 0 0 1 1 ad1 0 1 0 1 adc mode measure rssi battery voltage temp sensor to external pin rb2 0 0 rb1 0 1 readback mode afc word adc output 1 1 0 1 filter cal silicon rev rb3 0 1 readback disabled enabled 0 5876-0 37 figure 69. register 7readback setup register map readback of the measured rssi value is valid only in rx mode. readback of the battery voltage, temperature sensor, or voltage at the external pin is not valid in rx mode. to read back the battery voltage, the temperature sensor, or the voltage at the external pin in tx mode, users should first power up the adc using r8_db8 because it is turned off by default in tx mode to save power. for afc readback, use the following equations (see the readback format section): freq rb [hz] = ( afc_readback demod clk )/2 18 v battery = battery_voltage_readback /21.1 v adcin = adcin_voltage_readback /42.1 temperature [c] = ?40 + (68.4 ? temp_readback ) 9.32
adf7021 rev. a | page 55 of 64 register 8power-down test register pd1 pd3 pd4 pd5 db8 db7 db6 db5 db4 db3 db2 c2 (0) c1 (0) control bits db1 db0 c3 (0) c4 (1) log_amp_ enable synth_ enable reserved lna/mixer_ enable filter_ enable adc_ enable demod_ enable tx/rx_switch_ enable pa_enable_ rx_mode counter_ reset rx_reset cr1 db15 db14 db13 db12 db11 le1 pd6 db10 db9 sw1 pd7 pd7 0 1 pa (rx mode) pa off pa on cr1 0 1 counter reset normal reset demod reset cdr reset sw1 0 1 tx/rx switch default (on) off pd6 0 1 demod enable demod off demod on pd5 0 1 adc enable adc off adc on pd1 0 1 synth status synth off synth on pd3 0 1 lna/mixer enable lna/mixer off lna/mixer on pd4 0 1 filter enable filter off filter on le1 0 1 log amp enable log amp off log amp on 05876-038 figure 70. register 8power-down test register map it is not necessary to write to this register under normal operating conditions. for a combined lna/pa matching network, db11 should always be set to 0, which enables the internal tx/rx switch. this is the power-up default condition.
adf7021 rev. a | page 56 of 64 05876-03 register 9agc register 9 agc_high_threshold lna_ gain agc_ mode filter_ gain lna_ current filter_ current mixer_ linearity lna_mode agc_low_threshold address bits fg2 fg1 gl5 gl6 gl7 gh1 gh5 gh6 gm1 gm2 lg1 lg2 gh7 gh2 gh3 gh4 gl4 gl3 c2 (0) c1 (1) c3 (0) c4 (1) gl1 gl2 fi1 lg1 ml1 li1 li2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 fi1 0 1 filter current low high 0 1 2 3 agc mode auto agc manual agc freeze agc reserved fg2 0 0 1 1 fg1 0 1 0 1 filter gain 8 24 72 invalid lg2 0 0 lg1 0 1 lna gain 3 10 1 1 0 1 30 invalid gl3 0 0 0 1 . . . 1 1 1 gl1 1 0 1 0 . . . 1 0 1 agc low threshold 1 2 3 4 . . . 61 62 63 gl2 0 1 1 0 . . . 0 1 1 gl7 0 0 0 0 . . . 1 1 1 gl6 0 0 0 0 . . . 1 1 1 gl5 0 0 0 0 . . . 1 1 1 gl4 0 0 0 0 . . . 1 1 1 gh3 0 0 0 1 . . . 1 1 0 gh1 1 0 1 0 . . . 0 1 0 agc high threshold 1 2 3 4 . . . 78 79 80 gh2 0 1 1 0 . . . 1 1 0 gh7 0 0 0 0 . . . 1 1 1 gh6 0 0 0 0 . . . 0 0 0 gh5 0 0 0 0 . . . 0 0 1 gh4 0 0 0 0 . . . 1 1 0 li2 0 li1 0 lna bias 800a (default) lg1 0 1 lna mode default reduced gain ml1 0 1 mixer linearity default high figure 71. register 9agc register map in receive mode, agc is set to automatic agc by default on power-up. the default thresholds are agc_low_threshold = 30 and agc_high_threshold = 70. see the rssi/agc section for details. it is only necessary to program this register if agc settings, other than the defaults, are required. agc high and low settings must be more than 30 apart to ensure correct operation. an lna gain of 30 is available only if lna_mode (db25) is set to 0.
adf7021 rev. a | page 57 of 64 register 10afc register 0 5876-0 40 ki kp afc scaling_factor max_afc_range afc_en address bits kp3 kp2 ma3 m4 m5 m6 m7 m11 m12 ki2 ki3 ki4 kp1 ki1 m8 m9 m10 m3 m2 ma4 ma5 c2 (1) c1 (0) c3 (0) c4 (1) ae1 m1 ma2 ma6 ma7 ma8 ma1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 kp1 0 1 . 1 2^0 2^1 ... 2^7 ae1 0 1 afc enable off afc on ma3 0 0 0 1 . . . 1 1 ma1 1 0 1 0 . . . 1 0 max afc range 1 2 3 4 . . . 253 254 ma2 0 1 1 0 . . . 0 1 ma8 0 0 0 0 . . . 1 1 1 1 255 1 1 ... ... ... ... ... ... ... ... ... ... 0 0 . 1 0 0 . 1 ... kp2 kp3 kp ki1 0 1 . 1 2^0 2^1 ... 2^15 0 0 . 1 0 0 . 1 ki2 k i3 ki ki4 0 0 . 1 m3 0 0 0 1 . . . 1 1 m1 1 0 1 0 . . . 1 0 afc scaling factor 1 2 3 4 . . . 4093 4094 m2 0 1 1 0 . . . 0 1 m12 0 0 0 0 . . . 1 1 1 1 4095 1 1 ... ... ... ... ... ... ... ... ... ... ... figure 72. register 10afc register map the afc_scaling_factor can be expressed as ? ? ? ? ? ? ? ? = 5002 _ _ 24 the settings for ki and kp affect the afc settling time and afc accuracy. the allowable range of each parameter is ki > 6 and kp < 7 the recommended settings to give optimal afc performance are ki = 11 and kp = 4. to tradeoff between afc settling time and afc accuracy, the ki and kp parameters can be adjusted from the recommended settings (staying within the allowable range) such that afc correction range = max_afc_range 500 hz when the rf_divide_by_2 (r1_db18) is enabled, the programmed afc correction range is halved. the user accounts for this halving by doubling the programmed max_afc_range value. signals that are within the afc pull-in range but outside the if filter bandwidth are attenuated by the if filter. as a result, the signal can be below the sensitivity point of the receiver and, therefore, not detectable by the afc.
adf7021 rev. a | page 58 of 64 05876-041 register 11sync word detect register pl2 0 0 1 1 pl1 0 1 0 1 sync byte length 12 bits 16 bits 20 bits 24 bits mt2 0 0 1 1 mt1 0 1 0 1 matching tolerance accept 0 errors accept 1 error accept 2 errors accept 3 errors sync_byte_sequence control bits sync_byte_ length matching_ tolerance mt2 sb1 sb2 sb3 sb4 sb5 sb6 sb7 sb8 sb9 sb10 sb11 sb12 sb13 sb14 sb15 sb16 sb17 sb18 sb19 sb20 sb21 sb22 sb23 sb24 mt1 c2 (1) c1 (1) c3 (0) c4 (1) pl1 pl2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 figure 73. register 11sync word detect register map register 12swd/threshold setup register data_packet_length control bits lock_ threshold_ mode swd_mode il2 il1 c2 (0) c1 (0) c3 (1) c4 (1) lm1 lm2 db15 db14 db13 db12 db11 db10 db9 db8 dp8 dp7 dp6 dp5 dp4 dp3 dp2 dp1 db7 db6 db5 db4 db1 db0 db2 db3 lock threshold mode 0 threshold free running 1 lock threshold after next syncword 2 lock threshold after next syncword for data packet length number of bytes 3 lock threshold data packet length 0 invalid 1 1 byte ... ... 255 255 bytes swd mode 0 swd pin low 1 swd pin high after next syncword 2 swd pin high after next syncword for data packet length number of bytes 3 interrupt pin high 0 5876-042 figure 74. register 12swd/threshold setup register map lock threshold locks the threshold of the envelope detector. this has the effect of locking the slicer in linear demodulation a nd locking the afc and agc loops when using linear or correlator demodulation.
adf7021 rev. a | page 59 of 64 05876-043 register 133fsk/4fsk demod register refer to the receiver setup section for information about programming these settings. 3fsk_cdr_threshold viterbi_ path_ memory 3fsk/4fsk_ slicer_threshold control bits 3fsk_viterbi_ detector phase_ correction 3fsk_preamble_ time_validate st4 st5 st6 st7 vd1 pc1 vm1 vm2 vt1 vt2 vt3 vt4 vt5 vt6 vt7 st3 c2 (0) c1 (1) c3 (1) c4 (1) st1 st2 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db1 db0 db2 db3 ptv1 ptv2 ptv3 ptv4 db24 db23 db22 db25 4 bits 0 0 1 1 vm2 viterbi path memory vm1 0 1 0 1 6 bits 8 bits 32 bits phase correction 0 disabled 1 enabled pc1 3fsk viterbi detector 0 disabled 1 enabled vd1 vt3 0 0 0 . . 1 vt1 1 0 1 . . 1 3fsk cdr threshold 1 2 3 . . vt2 0 1 1 . . 1 vt7 0 0 0 . . 1 ... ... ... ... ... ... ... 127 00 0 ... 0 off st3 0 0 0 . . 1 st1 1 0 1 . . 1 slicer threshold 1 2 3 . . st2 0 1 1 . . 1 st7 0 0 0 . . 1 ... ... ... ... ... ... ... 127 00 0... 0 off ptv3 0 0 0 . . 1 ptv1 1 0 1 . . 1 3fsk premable time validate 1 2 3 . . ptv2 0 1 1 . . 1 ptv4 0 0 0 . . 1 15 00 0 0 0 figure 75. register 133fs k/4fsk demod register map
adf7021 rev. a | page 60 of 64 register 14test dac register test_dac_gain test dac offset test tdac en ed_peak_ response ed_leak_ factor pulse_ extension address bits tg3 tg2 er2 to4 to5 to6 to7 to11 to12 to14 to15 to16 tg1 to13 to8 to9 to10 to3 to2 ef1 ef2 c2 (1) c1 (0) c3 (1) c4 (1) te1 to1 er1 ef3 pe1 pe2 tg4 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 pulse extension 0 1 2 3 no pulse extension extended by 1 extended by 2 extended by 3 ed peak response 0 1 2 3 full response to peak 0.5 response to peak 0.25 response to peak 0.125 response to peak test dac gain 0 1 ... 15 no gain 2^1 ... 2^15 ed leak factor 0 1 2 3 4 5 6 7 leakage = 2^?8 2^?9 2^?10 2^?11 2^?12 2^?13 2^?14 2^?15 05876-044 figure 76. register 14test dac register map the demodulator tuning parameters, pulse_extension, ed_leak_factor, and ed_peak_response, can only be enabled by setting r15_db[4:7] to 0x9. while the correlators and filters are clocked by demod clk, cdr clk clocks the test dac. note that although the test dac functions in regular user mode, the best performance is achieved when the cdr_clk is increased to or above the frequency of demod clk. the cdr block does not function when this condition exists. using the test dac to implement analog fm demod and measuring snr t he test dac allows the post demodulator filter out for both linear and correlator demodulators to be viewed externally. the test dac also takes the 16-bit filter output and converts it to a high frequency, single-bit output using a second-order, error feedback - converter. the output can be viewed on the swd pin. this signal, when filtered appropriately, can then be used to do the following: programming register 14 enables the test dac. both the linear and correlator/demodulator outputs can be multiplexed into the dac. register 14 allows a fixed offset term to be removed from the signal (to remove the if component in the ddt case). it also has a signal gain term to allow the usage of the maximum dynamic range of the dac. ? monitor the signals at the fsk post demodulator filter output. this allows the demodulator output snr to be measured. eye diagrams of the received bit stream can also be constructed to measure the received signal quality. ? provide analog fm demodulation.
adf7021 register 15test mode register rx_test_ modes tx_test_ modes - _test_ modes pfd/cp _test_ modes pll_test_ modes analog_test_ modes clk_-mux force_ld high reg 1_pd cal_ override address bits pm4 pm3 am3 tm1 tm2 tm3 sd1 pc2 pc3 cm2 cm3 pm1 pm2 cm1 sd2 sd3 pc1 rt4 rt3 am4 fh1 rd1 co2 co1 c2 (1) c1 (1) c3 (1) c4 (1) rt1 rt2 am2 am1 db16 db15 db14 db17 db20 db19 db18 db21 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db22 db23 db24 db26 db27 db28 db25 db1 db0 db2 db3 db29 db30 db31 analog test modes 0 band gap voltge 140 a current from reg4 2 filter i channel: stage 1 3 filter i channel: stage 2 4 filter i channel: stage 1 5 filter q channel: stage 1 6 filter q channel: stage 2 7 filter q channel: stage 1 8 adc reference voltage 9 bias current from rssi 5 a 10 filter coarse cal oscillator o/p 11 analog rssi i channel 12 oset loop +ve fback v (i ch) 13 summed o/p of rssi rectifier+ 14 summed o/p of rssi rectifier? 15 bias current from bb filter cal override 0 auto cal 1 override gain 2 override bw 3 override bw and gain pfd/cp test modes 0 default, no bleed 1 (+ve) constant bleed 2 (?ve) constant bleed 3 (?ve) pulsed bleed 4 (?ve) pulse bld, delay up? 5cppumpup 6cptri-state 7cppumpdn reg1 pd 0normal 1pwrdwn force ld high 0normal 1 force - test modes 0 default, 3rd order sd, no dither 11st ordersd 2 2nd order sd 3 dither to first stage 4 dithertosecondstage 5 dither to third stage 6dither 8 7dither 32 tx test modes 0 tx carrier only 1 tx +ve tone only 2 tx ?ve tone only 3 tx "1010" pattern 4 tx pn9 data, at programed rate 5 tx sync byte repeatedly 6 rx test modes 0normal 1 sclk, sdata -> i, q 2 reverse i,q 3 linear slicer on rxdata 4 correlator slicer on txrxdata additional filtering on i, q envelope detector watchdog disabled reserved enable reg 14 demod parameters prohibit calactive enable demod during cal force calactive 5 6 i,q to txrxclk, txrxdata 7 8 9 10 11 12 power down ddt and ed in t/4 mode 13 14 15 pll test modes 0 normal operation 1rdiv 2ndiv 3 rcntr/2 on muxout 4 ncntr/2 on muxout 5 acntr to muxout 6 pfd pump up to muxout 7 pfd pump dn to muxout 8 sdata to muxout (or sread?) 9 analog lock detect on muxout 10 end of coarse cal on muxout 11 end of fine cal on muxout 12 13 test mux selects data 14 lock detect percision 15 reserved rev. a | page 61 of 64 05876-045 clk muxes on clkout pin 0 1 2 3 4 5 6 7 sdata to cdr force new prescaler config. for all n normal operation normal, no output demod clk cdr clk seq clk bb offset clk sigma delta clk adc clk txrxclk 3fsk slicer on txrxdata figure 77. register 15test mode register map
adf7021 rev. a | page 62 of 64 outline dimensions pin 1 indicator top view 6.75 bsc sq 7.00 bsc sq 1 48 12 13 37 36 24 25 0.30 0.23 0.18 4.25 4.10 sq 3.95 0.50 0.40 0.30 0.50 bsc 12 max 0.20 ref 0.80 max 0.65 typ 1.00 0.85 0.80 5.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max pin 1 indicato r coplanarity 0.08 seating plane exposed pad (bottom view) compliant to jedec standards mo-220-vkkd-2 0.25 min figure 78. 48-lead lead frame chip scale package [lfcsp_vq] 7 mm 7 mm body, very thin quad (cp-48-3) dimensions shown in millimeters ordering guide model temperature range packag e description package option ADF7021BCPZ 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-3 ADF7021BCPZ-rl 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-3 ADF7021BCPZ-rl7 1 ?40c to +85c 48-lead lead frame chip scale package [lfcsp_vq] cp-48-3 eval-adf70xxmbz 1 control mother board eval-adf70xxmbz2 1 evaluation platform eval-adf7021dbjz 1 426 mhz to 429 mhz daughter board eval-adf7021dbz2 1 860 mhz to 870 mhz daughter board eval-adf7021dbz3 1 431 mhz to 470 mhz daughter board 1 z = rohs compliant part.
adf7021 rev. a | page 63 of 64 notes
adf7021 rev. a | page 64 of 64 notes ?2007 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05876-0-9/07(a)

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